I am trying to write a FSM in System Verilog that acts as a password detector. The password will be inputted using 4 buttons labeled b1, b2, b3, b4. The correct passcode is b1-b2-b3-b4. This is my logic and code for the first two states:
module FSM(
input b1, b2, b3, b4,
output logic unlock
typedef enum {STA, STB, STC, STD, STE} STATES;
STATES NS, PS = STA;
always_ff@(posedge clock)
begin
PS <=NS;
end
always_comb
begin
unlock = 0;
case(PS)
STA:
begin
if (b1 == 1'b1) // If button one is pressed
begin
NS = STB;
else:
NS = STA;
STB:
begin
if (b2 == 1'b1) // If button two is pressed
begin
NS = STC;
else if (b1 == 1 | b3 == 1 | b4 == 1) // if any other button is pressed go to stateA
begin
NS = STA;
else // stay in state B until a button is pressed
begin
NS = STB;
end
My FSM goes from STA to STB fine, but after inputting the correct button to go from STB to STC, the FSM goes back to STA. If I hold all the buttons down in the correct sequence at once, it will go to the last state. Could someone explain the error in my logic or if there is a better way to implement this?