Verilog Synchronous state machine

Question

I'm trying to design this state machine in verilog:

I was have:

   `timescale 1ns/1ns
module labEightMachine(y, x,clk,clr)
        output      y;
        input [1:2] x;
        input       clk, clr;
        reg [1:2]   q;
        reg         y;
        reg         nX;
        always @ (posedge clk)
            begin
            if(clr)
                {q}<=2'b00;

            else
                q<= {nX}
            end
        always @(y,x)
        begin
        if(q==2'b00)
            if(x==2'b00)
                q<=2'b00;
            else
                q<=2'b01;
                y<=1;
        if(q==2'b01)
            if((x==2'b00)||(x==2'b01))
                q<=2'b00;
                y<=0;
            else
                q<=2'b11;
                y<=0;
        if(q==2'b11)
            if(x==2'b10)
                q<=2'b10;
                y<=1;
            else
                q<=2'b00;
                y<=0;
        if(q==2'b10)
            q<=2'b00;
                y<=0;
        end
endmodule

If any one could help by telling me where it is incorrect, that would be greatly appreciated. The state machines confuse me and I'm not sure that I am reassigning everything correctly.

For easier to understand FSM use a case statements, [asic-world](http://www.asic-world.com/tidbits/verilog_fsm.htm). — Morgan, Oct 29 '15 at 08:17

score 1 · Answer 1 · answered Oct 29 '15 at 04:09

Applying stimulus is always a better way to check your code. Leaving the syntax errors of semi-colons/begin-end and all that, a couple of immediate logical errors I can see are as below.

The declaration reg nX declares a variable of single bit width. On the contrary, q is declared as reg [1:2] q, of two bits width.

Secondly,q is driven from two always blocks. If clr is LOW, then q is driven by nX. While, nX is never driven by any signal. So, the output will be x majority of times (leaving those race-conditions). Multiple driver issues.

Thirdly, it would be better to use if--else if--else ladder instead of multiple ifs. This will make the next_state logic clear.

A better FSM, might have two always blocks and one output logic block. One for sequential logic and other for combinational logic. Sequential block is used to update the current_state value by the next_state value. While, a combinational block is used to update the next state value according to inputs. The output logic must either have a separate block of continuous assignments or a procedural block.

Also, it might be convenient to use a case statement for next_state logic. This will be useful when too many states are interacting with each other in a single FSM. Using default in case statement is inevitable.

For further information on efficient FSM coding styles, refer to CummingsSNUG1998SJ_FSM paper and CummingsSNUG2000Boston_FSM paper.

Verilog Synchronous state machine

1 Answers1