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I'm trying to implement two-digit-bcd-counter in VHDL, by referring to this diagram: enter image description here

This is my code for it:

library ieee;
use ieee.std_logic_1164.all;

entity two_digit_bcd_counter is
port(
    v_cc  : in std_logic;
    clk   : in std_logic;
    clr   : in std_logic;
    bcd0 : out std_logic_vector(3 downto 0);
    bcd1 : out std_logic_vector(3 downto 0)
);
end two_digit_bcd_counter;

architecture structural of two_digit_bcd_counter is

signal y1, y2, y3, y4, y5, y6, y7, y8 : std_logic;
signal output0, output1 : std_logic_vector(3 downto 0);

component decade_counter is
port(
    v_cc  : in std_logic;
    clk   : in std_logic;
    clr   : in std_logic;
    Q_out : out std_logic_vector(3 downto 0)
);
end component;
     
begin
    bcd_counter_0: decade_counter port map(v_cc => v_cc, clk => clk, clr => y8, Q_out => output0);
    bcd_counter_1: decade_counter port map(v_cc => y3 , clk => clk, clr => y7, Q_out => output1);
     
     y1 <= output0(0);
     y2 <= output0(3);
     y4 <= output1(0);
     y5 <= output1(3);
     
     y3 <= y1 and y2;
     y6 <= y4 and y5 and y3;
     y8 <= y3 or clr;
     y7 <= y6 or clr;
     
     bcd0 <= output0;
     bcd1 <= output1;
     
end structural;
  • The test-bench I used can be found here.
  • Code for component decade_counter can be found here.
  • Code for component t_flip_flop used in decade_counter can be found here. (There isn't any probelm in this one for sure)

The output waveform I received for this is:

As you can see only the lower order digit is working as expected
As you can see only the lower order digit of output is working as expected, but the higher order digit output is just 0000 always. Can anyone help me with fixing this?

theCursedPirate
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  • Routing FF output signal to clock input as in `decade_counter`.`tff1` it's bad practice for datapath logic – G. C. Mar 08 '22 at 09:26
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    Provide a [mcve] in the question itself. Not via links. Your testbench doesn't replicate your waveform. – user16145658 Mar 08 '22 at 09:40
  • The code in the question itself works as 'minimal reproducible example', those links are just in case if someone thinks the problem lies in the other modules. – theCursedPirate Mar 08 '22 at 09:45
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    Without the testbench and `decade_counter`, the code supplied is not complete nor reproducible – Tricky Mar 08 '22 at 09:55
  • So, I should put all the codes in the link here? but that will make the post really long. The tesbench was generated using software and it's very long. – theCursedPirate Mar 08 '22 at 10:02
  • Include the t_flip_flop. 180 lines, some that can be eliminated (9 comment lines). Don't use tabs and you reduce the character count by getting rid of trailing spaces. (There's a 30K character post size limit). The idea is that future readers can use your question and any accepted up voted answer as a search resource to answer similar or identical questions instead of asking yet again. You've got a [XY Problem](https://meta.stackexchange.com/questions/66377/what-is-the-xy-problem/66378#66378) you covered up by asking a too broad question. – user16145658 Mar 08 '22 at 10:14
  • You really want to use a synchronous load to avoid glitches in implementations due to delay mismatches @G.C. alludes to. For VHDL simulation you need the reset. – user16145658 Mar 08 '22 at 10:18

1 Answers1

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y3 is going to clear itself, through y8 in an asyncnhronous way.

This design is generating a glitch on y3 longh enough to self reset, but it will never be sampled on bcd_counter_1

G. C.
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  • So, the circuit diagram itself is flawed? But then it is the only diagram you get if you search for 2-digit-bcd-counter. Or is there something wrong in the way I implemented the circuit? – theCursedPirate Mar 08 '22 at 09:37
  • `Load` signal and `enable` signals are not optional, they are clearly shown on diagram but you skipped them in the implementation. Both must be synchronous – G. C. Mar 08 '22 at 09:47
  • I represented `enable` port by `v_cc`, and `load` port by `clear`, thinking they're the same. Is there something wrong in these ports. – theCursedPirate Mar 08 '22 at 09:50
  • As I can see `V_cc`=`D`, `clr` is the async reset port, usefull but not shown on diagram. `Enable` and `Load` missing. Be more compliant to diagram, even with port-names, it will be easier to debug for yourself. – G. C. Mar 08 '22 at 09:53
  • It's easier to see in a decimal radix but your 'decade counter' [doesn't reach 9](https://i.stack.imgur.com/X0Mln.jpg). Provide a [mcve] in your question (and fix the testbench). Consider actually troubleshooting by looking down in the hierarchy. – user16145658 Mar 08 '22 at 09:54
  • I've replaced the testbench, with a new one, hopefully it will represent the diagram. It should because I autogenerated it using quartus prime's tool from the exact diagram in the picture. – theCursedPirate Mar 08 '22 at 10:00
  • The picture without the reset? – user16145658 Mar 08 '22 at 10:14