Vitis HLS pro
Vitis HLS can provide:
- A packaged IP already for you with no further modifications
- The generated code might use primitives and structures to facilitate the synthetizer when generating the netlist.
- AXI interfaces (Stream, Lite, Full) ready for integration in your block design.
- Nice RTL/C cosimulation to detect early bugs.
So if you are targeting Xilinx devices I would suggest C++ HLS with Vitis.
HLS challenges
Be aware that HLS is quite difficult to master, and that's because the procedural nature of C++ is fundamentally different from HDLs. This makes generation of conditional branches not clear. Be wary of using too many branches in your code.
Try to keep a "dataflow" style in mind, where data is streamed in and an output is produced in a clear, pipelined, streamed fashion.
Be wary also of memory accesses and latency throughout your system, sometimes the bottlenecks aren't where you think they are.
Alternatives
Lastly, a suggestion about using HLS at all. There are many libraries in FPGA already done (for instance here) that use native FPGA HDL but provide you accelerators for the basic blocks of computer vision to use within your software. You might just want to use them without need to reinvent the wheel.
I hope it helps!