SystemVerilog Assertion does not fail when it should

Question

I have a simple assertion as follows:

$rose(req) |=> !req[*1:10] until ack ##1 !ack;

As I understand, on detection of $rose(req), the assertion should check for !req to be low consecutively for max 10 clocks OR -until- ack arrives (ack=1). Once ack is true, it should de-assert the very next clock.

My test starts with $rose(req); then keep !req asserted for a few clocks (less than 10) and then drives ack=1. Then, I keep ack=1 for 4 clocks. It does not go low the very next clock, as the assertion requires. Still, the assertion does not fail. The thread "!req[*1:10] until ack" seems to keep firing, even after ack has arrived and the 'until' condition is satisfied.

Any ideas why the assertion does not fail?

Here's the EDA playground link that simulates the scenario.

EXAMPLE

Answer 1

You assertion is totally valid!

You are giving no information about ack signal during the !req[*1:10] phase.

The simulator finds a sequence where req=0 for some clock cycles (max 10), then find ack=1 followed by ack=0;

What you want can be obtained with:

$rose(req) |=> (!ack throughout !req[*1:10]) ##1 ack ##1 !ack; 

I would not use until ack here, just ##1 ack

Answer 2

G.C.'s solution works.

I found another solution as well.

@(posedge clk) $rose(req) |=> first_match(!req[*1:10] ##1 ack) ##1 !ack;