How do I include the base.dtbo/pl-final.dts for a reconfigurable FPGA in my Yocto Honister image (meta-xilinx xlnx-rel-v2022.1_update2)?

Question

When porting to a new Yocto Honister distro and the meta-xilinx metalayer xlnx-rel-v2022.1_update2, the base.dtbo device tree overlay is not generated anymore for dynamic FPGA reprogramming. How do I get the generation running again?

Answer 1

TL;DR: Add fpga-overlay to your MACHINE_FEATURES

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The dynamic reconfigurator fpga-manager, recipe fpga-manager-util.bb creates the base.dtbo from the file pl-final.dtbo. This file has to be created from the device-tree.bb recipe. For the pl-final.dtbo to exist, a pl-final.dts has to be created via the call xsct -sdx -nodisp dtgen.tcl ... -yamlconf device-tree.yaml. The referenced YAML file contains the information, whether pl-final.dts has to be generated.

This YAML file is generated via bitbake -c create_yaml device-tree. Whether the pl-final.dts is created, is queried by the variable YAML_ENABLE_DT_OVERLAY. In the old meta-xilinx layer, this was tied to FPGA_MNGR_RECONFIG_ENABLE, which was active by default. In the new xlnx-rel-v2022.1_update2 layer, this is tied to fpga-overlay being in your MACHINE_FEATURES.

So to get the base.dtbo again, add fpga-overlay to your MACHINE_FEATURES