Xilinx Alveo U50 ES3 FPGA, FPGA_RXD_MSP pin meaning?

Question

I found on https://github.com/Xilinx/XilinxBoardStore/blob/2020.1.1/boards/Xilinx/au50/production/1.0/part0_pins.xml

two pin names I dont understand. What are purpose of

<pin index="9"   name ="FPGA_TXD_MSP"  iostandard="LVCMOS18" loc="BB25"/>
<pin index="10"  name ="FPGA_RXD_MSP"  iostandard="LVCMOS18" loc="BB26"/> 

in line 29?

Best'

Answer 1

I have found some information about the pin on the alveo product guide, section Maintenance Connector Interface, which I quote:

The Alveo U50 accelerator card provides access to the FPGA through the JTAG interface using a debug and maintenance board (DMB) connected to the 30-pin maintenance connector. The connector pinout supports three UART debug interfaces: PMBus, FPGA JTAG, and satellite controller JTAG.

(From here you can dive deeper into the UG1377)

By looking at another u50 alveo PG we can find more info about the satellite controller (page 5).

A TI MSP432 satellite controller resides on the U50/U50 LV card to control and monitor voltages, currents and temperatures

By looking at the picture, , it seems that the PINs you are searching for are UART pins (TX,RX) to communicate to the TI satellite controller from directly the FPGA.