Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
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1 answer
Length of the longest consecutive 1's in a binary number
I need to implement a digital logic circuit with logic gates such as AND, OR, NOT, ADDER (and so on..), that gets an 8 bits binary number and return the number of the longest consecutive 1's in the input.
For example:
11110011 - will return…
CrazyPhrog
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1 answer
HDL counter and flag coding style
In Verilog/VHDL, lets say I have a 4 bit counter, and a flag that should be asserted when the counter equals between 4 and 8. There are two ways to implement this
if((cntr>=4)&&(cntr<8))
flag <=1;
else
flag <= 0;
Or, I could…
David
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7 answers
And / or in java
im having a problem in my java exercice
the question is saying
The program will end when the sum of even is >= 50 or the sum of odd is >= 49.
so while solving it i tried to use
while (sumeven < 50 || sumodd < 49 )
and it didnt worked at all but…
Ali Zgheib
- 15
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0
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1 answer
Analyzing output of a digital circuit with MUX
I have this circuit:
I need to:
find the output z
make it a canonical SOP
writing the minimal POS
finally expressing z with only NAND ports.
I'd like to receive suggestion(tricks?)/correction on my attempt as I am not 100% sure about it.
Z…
J Alan
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1 answer
How to implement hardware that remembers previous value in digital logic design?
I am trying to design the following:
The datapath of an octal calculator which has a 24-bit input register in
reg and a 24-bit accumulator acc.
The contents
of both registers are displayed as eight octal (radix-8) digits. Both are cleared on…
aa1
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Why do we use complements to perform subtraction operation in computer systems?
Why do we have to use complements (e.g 2's complement, 10's complement etc) in computer systems to perform subtraction operations? Just like circuits for addition operations(adders) , we do have circuits for subtraction(subtractors), right?
Waqar Danish
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How do I encrypt a 4 bit number using multiple patterns?
I'll preface this by saying I Don't want the answer, just a nudge in the right direction.
The conversion table for the encryption is as follows:
Input --> Output
0 --> 15
1 --> 14
2 --> 13
3 --> 12
4 --> 0
5 --> 1
6 --> 2
7 --> 3
8 --> 7
9 --> 6
10…
Zantorym
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two's complement of signed values in subtraction
In a VHDL assignment, I have to make an ALU which outputs the result of the subtraction and two's complement and some other operations on 16bit inputs. In a way that the rtl code is compared with the functional one.
In the functional code, I have…
syzd
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Design a (r-1)'s complement system with minimum cost when r = 5 using any 2-input AND, 2-input OR and NOT gate
after making the truth table I am unable to make the appropriate circuit diagram.
I don't know how am I supposed to produce the r-1's complement as the output.
AMT
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2 answers
Do we use Gray Counter to avoid metastability in Asynch FIFO?
What happens when 1 bit which is changing in Gray Code counter goes into metastability ? Why it isn't a problem in asynchronous FIFO?
Rottenengg
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2 answers
SystemVerilog: S-R Latch doesn't work correctly
Here is my gate-level description of an S-R latch:
module SR_Latch_Nand(input S, R, C, output Q, QB);
wire s1, r1;
nand #8 n1(r1, R, C);
nand #8 n2(s1, S, C);
nand #8 n3(QB, R, Q);
nand #8 n4(Q, S, QB);
endmodule
and here is test bench…
Ju Bc
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1 answer
SystemVerilog priority modifier usage
I'm reading about SV priority keyword. I found following example in on of the papers written by Sutherland:
I'm not quite sure why we can see simulation synthesis mismatch if {priority} is NOT used. Lets assume we don't use {priority} and {IRQ} is…
newbie
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2 answers
Boolean algebra minimization using NAND only
Can anyone explain how the boolean expression is simplified in the last step?
Original Question:
Realize X=a´b´d´+b´cd´+a´b´c+a´cd´+abc´+abd+bc´d+ac´d using
minimum number of 2-input NAND gates. Assume that double-rail inputs
are available. No gate…
Ameer Hamza
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- 1
0
votes
1 answer
SystemVerilog: How to convert a binary vector to integer
I have an 8-bit input A and also 3-bit input n. I want to shift A n times to left or right but this code doesn't seem to work (the output is x):
w = A << n;
But when i put an integer like 2 instead of n, the code works without problem. So how to…
Ju Bc
- 173
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0
votes
1 answer
multipile 8bit registers connected to the same output (VHDL)
I create a 64bytes RAM using two 3bit address registers and cross bar of the 3 bit registers using two 3to8 decoders. Here is the VHDL code:
library ieee;
use ieee.std_logic_1164.all;
entity ram88 is
port(a : in std_logic_vector (2 downto 0);
…
argasm
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