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Questions tagged [digital-logic]

Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)

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Making K-maps with S2, S1, S0 (seven states), one button input, and four outputs

So my state diagram has seven states (000 to 110), an input B button, and four outputs P, Q, R, and S. I've made the truth table, which has 16 rows (two of which have Xs). I'm supposed to make 7 K-Maps out of this, S2' S1' S0' P Q R and S. I…
sumitz1212
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How to define clock input in Xilinx

Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course that is due soon, where my partner, who was supposed to take care of the Xilinx simulations decided to bail on me. So here I am trying to figure it out…
seventeen
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Frequency divisor in verilog

i need a frequency divider in verilog, and i made the code below. It works, but i want to know if is the best solution, thanks! module frquency_divider_by2 ( clk ,clk3 ); output clk3 ; reg clk2, clk3 ; input clk ; wire clk ; initial clk2 =…
Guilherme Stéfano
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Structure of VHDL code for barrel shifter with behavior architecture

I am trying to build a 16 bit barrel shifter with left and right shift capabilities. I am having some issues with how to structure the code so that it will do what I think I want to do. I have an opcode input that decides on the direction, an input…
user3120471
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Strange component in quartus RTL viewer using verilog

I'm learning verilog, and when i don't know how a circuit will work just looking in the verilog code, I go to RTL viewer to see the digital logic. But in this code a strange component appears and I don't know what is this component. Is a flip-flop,…
Guilherme Stéfano
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Arduino Digital Pins HIGH LOW output seem to be reversed

I've written a code last year which was working well at that time. However on loading the same code this time I am getting reversed output. That is, when the Digital Pin is set to HIGH, it return LOW and vice versa. digitalWrite(led, HIGH)…
rohan.k
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Chisel: how to avoid errors NO DEFAULT SPECIFIED FOR WIRE

I'm trying to implement a structured read port to Mem: class TagType() extends Bundle() { import Consts._ val valid = Bool() val dirty = Bool() val tag = UInt(width = ADDR_MSB - ADDR_LSB + 1) } object TagType { def apply() =…
Alexander Samoilov
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Chisel runtime error in test harness

This Chisel code works ok: chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module( new Cache(nways = 16, nsets = 32) )){c => new CacheTests(c)} However this one - a small variation - produces run-time error: val cache_inst =…
Alexander Samoilov
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Verilog: Store counter value when reset is asserted

I have the following verilog code. Idea is to store value of counter at the time of reset. However, I am not sure if it would be synthesizable(memories need synchronous reset). I get DRC violatins and the memory, bufreadaddr, bufreadval are all…
user763410
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Is it possible to avoid specifying a default in order to get an X in Chisel?

The following Chisel code works as expected. class Memo extends Module { …
dan
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Application of Barrel Shifter

I am doing a VLSI Project and I am implementing a Barrel Shifter using a tool called DSCH.The schematic for the same is realized using Transmission Gates. What the circuit does is, it ROTATES the 8 bit word(8-bit shifter) with as many rotations…
user1829886
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Race conditions

I'm currently stuck trying to understand two things related to race conditions. Issue 1: I have been presented with the following question: We consider the digital circuit and the value of its inputs a, and b as given below. For all logic gates, we…
methuselah
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distributive property for product of maxterms

I am unsure how to use the Distributive property on the following function: F = B'D + A'D + BD I understand that F = xy + x'z would become (xy + x')(xy + z) but I'm not sure how to do this with three terms with two variables. Also another small…
sam
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How can I determine the sop and pos part from a combined expression

(, , , ) = (′ + ′)( + ′)′ + ′(′ + ′) + ′ like this combined expression where SOP and POS are both available how can I know which are sop & which are pos? I am trying to find the sop & pos from this combined expression but I can't. We know (′ + ′)( +…
Mohit
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Using One's Complement In Place of Directly Subtracting Two Binary Numbers

I've decided to start learning some logic design recently. I'm current at the very first unit in the book I'm using (Fundamentals of Logic Design - 5th Edition if it's of any importance) and it's given me a series of questions to answer. Prior to…
ManedManRicky
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