Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
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How to simplify circuits
The answer to the question is A in case someone thinks Im cheating for a test or something. I really wan't to understand how to solve such questions. I am guessing there is some way to bring these brackets together and to get a simplified circuit…
user737163
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Implementation of 8:1 MUX using 3:8 decoders and 2 input gates
How do I implement a 8:1 MUX using 3:8 decoders and 2 input gates?
I know how a 8:1 MUX works and how a 3:8 decoder works but I am not able to understand the approach to convert the decoder to mux using 2 input AND or OR gates.
Our Sir told this…
Savannah Madison
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C/Digital Logic - Why are my zero-initialized variables changing value?
They're actually initialized to the character '0' (ie 48). I'm making a logic simulator and each bit is represented as a single char, either '0' or '1'. All of my other components have worked until I made an 8-bit selector.
This is the code for the…
Reuben Z
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How would you write a SystemVerilog Function that adds an even parity bit to a 7-bit vector?
Would you take a 7-bit logic variable as an input and return an 8-bit logic output with the parity bit being the MSB (leftmost bit) of the output?
In a system that uses even parity you want the total number of 1 bits in the output vector to be even,…
CEStudent
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Two ways to write pipeline in verilog, which one is better?
I learned two ways of writing pipeline(unblocking and blocking), I wonder which is better?
My personal opinion is that the second one is tedious and I don't understand why so many wire are needed.
Also, is there any standard style(template) of…
ChufanSuki
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I am writing a SystemVerilog Testbench for a module that models a schematic, but don't know why transcript window saying no connection to port Y?
The Following schematic is what I have modeled my module from. This is a SystemVerilog HW assignment in which we must use contiuous assignment(s). The signature model was given to us. Note there is no delays in the circuit. The problem I am having…
CEStudent
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How can I find the equation from this truth-table using k-map or QM method?
How can I find the equation from this truth table using k-map or QM method?
Shakel Chowdhury
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Testbench for FSM
I'm trying to implement a testbench for the following fsm in created in vhdl. The problem is that currently, I'm not seeing any state transitions in the test bench. The simulation stays at state 0.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use…
Tellrell White
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FSM for long bit sequence
Currently, I'm working on a mealy fsm that detects a 17 bit sequence 10100001010000001. Due to the length of the sequence, I'm having difficulty figuring out which state to return to when the input doesn't allow me to move on to the next state. Any…
Tellrell White
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Trouble creating finite state machine
I'm working on creating a state machine and vhdl code for a task I've been given. It involves a machine which uses a FPGA to control its functions. It has a 100 MHZ clock with 50% duty cycle. The user presses a button on the machine and a led is…
Tellrell White
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Not understanding vhdl online compiler error
i am using an inline compiler (https://www.edaplayground.com/) and im not understanding the online compilers error message. I am trying to build the boolean expression (a * !b) + (b * !c) + (!b * c).
My code is:
library IEEE;
use…
DEN
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What does shared memory do when they get 2 write request from 2 cores in RISC V multi core processor?
I'm just doing a project "design a dual-core processor based on RISC-V ISA no pipeline, no private or share cache and 2 cores are shared a data memory". I have designed RISC V single core processor and it's worked. There are something i don't…
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0 minus 0 gives carryout of 1 in adder-subtractor circuit
In this adder-subtractor design with the "M" input as the flag for subtraction, 0 minus 0 seems to provide the incorrect Cout. Let's assume that we're only using one full adder here (ignore A1/B1, A2/B2, A3/B3) for simplicity, and M=1, A0=0,…
platizin
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Digital logic Counters
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0, ...) is ? and also construct the circuit design.
My Approach:
I understand that minimum J&K Gate required is 3…
John Lucas
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VHDL Subtraction results in 'X' in the upper 4-bit of the results, how do I fix this?
I'm trying to implement a division algorithm in vhdl. To do that the first step is to double the amount of bits that are in the dividend and divisor. The next step is to perform a subtraction with these expanded values. When vhdl performs the…
Ben Rei
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