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I have this circuit:

enter image description here

I need to:

  1. find the output z
  2. make it a canonical SOP
  3. writing the minimal POS
  4. finally expressing z with only NAND ports.

I'd like to receive suggestion(tricks?)/correction on my attempt as I am not 100% sure about it.

Z output

Okay I have some doubts regard the second operand of z, the output of the MUX. Since a MUX it's just a OR of NANDs between input and control lines (here x1/x2) I skipped the 0s and come out with just x3* ~x1x2 ( since it's the position 01) and ~x3*x1x2. Is my logic right here?

z=x1x3+(~x1(x3 xor x2)) + (x3~x1x2+x1x2~x3)

Z as Canonical SOP

I just elaborated z (done the xor and multiplication):

z= x1x3+[~x1x2~x3+~x1~x2x3+~x1x2x3+x1x2~x3] = x1x2x3 + x1~x2x3 +[~x1x2~x3+~x1~x2x3+~x1x2x3+x1x2~x3]

Z as minimal POS

Once I had the canonical POS I just built the truth table, the only 0 where at 000/001 (~x3~x2~x1 / ~x3~x2x1) then I used a k-map and the minimal pos resulted: z=(x3+x2)

Expressing the whole thing with NANDs

I just started from the POS expression:

z = x3+x2 = NAND(~x3,~x2) = NAND(NAND(x3,x3),NAND(x2,x2))

J Alan
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1 Answers1

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I tackled your question using Logic Friday 1:

enter image description here

Resulting equations:

Entered by gate diagram:

Z = X1' X3' X2 + X1' X3 X2' + X1 X3' X2 + X1 X3 X2' + X1 X3 X2;

Minimized:

Z = X3' X2 + X3 X2' + X1 X2;

I share your doubts about the multiplexer. Depending on the numbering of the data inputs (0..3 or 3..0) and selection inputs (0..1 or 1..0), you arrive at different results.

To check my results, I wrote a truth-table using the signal numbers of my circuit diagram:

enter image description here

This confirmed the five minterms.

Using a Karnaugh map:

             x2x3
       00  01  11  10
      +---+---+---+---+
   0  | 0 | 1 | 0 | 1 |
x1    +---+---+---+---+
   1  | 0 | 1 | 1 | 1 |
      +---+---+---+---+

This leads to product-of-sums POS:

(x2+x3) & (x1+!x2+!x3)

and sum-of-products SOP:

x2!x3 + !x2x3 + x1x2

The SOP can be written as:

NAND(NAND(x2, !x3), NAND(!x2, x3), NAND(x1, x2))
Axel Kemper
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  • Our Z differs by one minterm that you miss while I don't: x3x2x1' which I get from the output of the multiplexer (second line: x1'x2x3). Now even if you chose a different numbering for the input, anyway you should have two minterms out of the MUX which would make six minterms (4 are from the other input in the final Z OR); so I think you maybe missed it while writing or you are wrong. Your minimized Z it's in SOP form which I didn't asked for, but I get a different result's there as well: x2+x3x2' – J Alan Mar 25 '18 at 14:00
  • I saw your edit, your logic it's right and I would end with your same results BUT I think the difference it's in the MUX: my control lines are x1x2 and assuming 0..3 order (and skipping 0) I have: x3x1'x2 + x3'x1x2. We both have the last one but not x3x1'x2 this - seems to me- it's because your MUX control lines are x2x1. So basically I think your circuit it's different from mine. Anyway thanks for your efforts and, matter of fact, showing that my methodology it's right. – J Alan Mar 25 '18 at 15:33