Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)
Questions tagged [digital-logic]
229 questions
3
votes
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Difference between shift adder and Serial Adder
Is shift adder and serial adder are same? I tried Google but I cannot understand difference. I have to use it in VHDL.
Thanks
user3696958
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3
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2 answers
Is I2C master to Master communication possible?
Is it possible for an I2C master device to communicate with another I2C master device ?
Thanks
user3433044
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3
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2 answers
Right Shift in java
I am just stuck with this small logic that i am not getting it right
int is 32 bits so suppose taking 20 in binary would be like
// 00000000000000000000000000010100
.. now if I perform rightshift operation say 4
int a = 20>>4;
//…
Mukesh Kumar Singh
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Chisel synthesized none neither for verilog nor for C++
For the following fragment Chisel synthesized none:
import Chisel._
import Node._
import scala.collection.mutable.HashMap
class PseudoLRU(val num_ways: Int) extends Module
{
val num_levels = log2Up(num_ways)
val io = new Bundle {
…
Alexander Samoilov
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3
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1 answer
It would be nice to have Vec[Mem] in Chisel
It would be nice to Vec[Mem] for say set-associative caches.
Unfortunately Chisel doesn't support Vec[Mem] construct:
val tag_ram2 = Vec.fill(num_ways) {Mem(new TagType(), num_sets , seqRead = true )}
Indeed:
inferred type arguments…
Alexander Samoilov
- 467
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3
votes
1 answer
Digital logic - mealy state machines?
I understand the way Mealy state machines work - the output logic is now a function of not just the current state but of the input directly as well.
But what is the advantage to this over Moore machines? Do people commonly use Mealy FSMs?
JDS
- 16,388
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2
votes
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How to create K-MAP from function
How can I create a K-MAP by looking at this function.I dont know how to create one
Emirhan Selim Uzun
- 632
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1 answer
How to create boolean data type to standard logic in VHDL
Is there an existing function within the regular std.logic library to convert a boolean data type to std logic in vhdl?
Tellrell White
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2
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2 answers
How to test modules with bundle/vec input?
How do you test modules with IO input port of type Vec, Bundle, or composition of these?
In other words, using PeekPokeTester, how do you properly poke() a port that is of type Vec, Bundle, or more complex composition of these two types? Thanks!
apen
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Are there any "easy" fast algorithms for a 16 bit by 16 bit 2's complement integer divider?
I am currently working on a school project and one of my tasks is to implement a 16-bit by 16-bit 2's complement integer divider as a digital logic circuit (in other words 16-bit input divided by another 16-bit input). The output is straightforward…
xavieremeralds
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How would you handle a special case in this digital logic system?
I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.
alt text…
e.James
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How is Carry Flag set when subtrahend is larger?
I know the Carry flag during SUB is set whenever the minuend is smaller than the subtrahend and a borrow is required, but haven't been able to find anything explaining this in more detail.
Since subtraction is actually just adding with two's…
cafekaze
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votes
3 answers
K-Map to solve algebraic reduction
I need help verifying an algebraic expression using K-Map.
The expression I'm posting was actually done by my professor, but for practice purpose I wanted to use the K-Map to verify that the answer is correct.
-> X • Y + X' • Y • Z' + Y • Z =
…
miiworld2
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votes
2 answers
What is the maximum number of inputs for any logic gate?
In the references that we use, I usually see either a 2 or 3-input logic gate. Four-input gates come by once in a while. However, is there a certain limit to the number of inputs a logic gate can have theoretically? I'm assuming in actual practice…
mitch08
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votes
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Overflow and carry flag
The context
I read in a textbook that...
An addition and subtraction cannot cause overflow. To quote,
"An overflow cannot occur after an addition if one number is positive and the other negative, since adding a positive number to a negative number…
Jacky Moon
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