In a VHDL assignment, I have to make an ALU which outputs the result of the subtraction and two's complement and some other operations on 16bit inputs. In a way that the rtl code is compared with the functional one.
In the functional code, I have used arithmetic operations like "+", "-" and ..., but in the rtl, I have used structural VHDL. That is why I have to be accurate so the results of these codes show the same output. I don't know what parts of the codes might be useful to share.
I am working on a vhdl code that subtracts two "signed" numbers (signed in two's complement format) in the structural form. Normally for subtracting two unsigned numbers, we change the second one to two's complement and add the numbers.
But, now that we have signed numbers, say we want to subtract two 16 bit signed numbers that the last MSB is the sign bit. How does two's complement work here? (Looking at here), if I want to have a - b (a and b are signed numbers) I should have:
a + (two's complement b)
or
a + (not b)?
(a and b are signed in two's complement format)