Do we use Gray Counter to avoid metastability in Asynch FIFO?

Question

What happens when 1 bit which is changing in Gray Code counter goes into metastability ? Why it isn't a problem in asynchronous FIFO?

[Electronics SE](https://electronics.stackexchange.com/) would be a better place for this question. — , Aug 05 '17 at 19:44

score 1 · Accepted Answer · answered Aug 08 '17 at 15:43

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You might want to take a look at Cliff Cummings's famous paper about Asynchronous FIFO Design.

answered Aug 08 '17 at 15:43

AndresM

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score 0 · Answer 2 · answered Aug 05 '17 at 07:23

I think asynchronous FIFO actually internally uses gray code counter to pass the write/read address pointer across the two clock domains.

You will have metastability issue if more than 1 bit is toggled in one clock domain, but no all the bits are captured by the other clock domain. One 1 bit can toggle in a gray code counter and the value stays. It does not matter when the 2nd clock samples the toggled bit from the 1st clock, it may be one cycle late but it doesn't matter.

So if rd pointer is late by 1 clock cycle, it would not create any pseudo full condition? — Rottenengg, Sep 14 '17 at 16:30

Do we use Gray Counter to avoid metastability in Asynch FIFO?

2 Answers2