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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

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chisel3: Want to use Vec, but need to use IndexedSeq

In generating a tapped shift register using "scanLeft", I needed to use a IndexedSeq of registers and explicit copying of the result of scanLeft to an output wire. Here are four examples (with testbench). Only the first one works. I like the second…
Steve Burns
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Chisel3 type mismatch with Array of FixedPoint

In Scala one way we could declare an ArrayBuffer of array of Doubles,Long and Boolean is as such: val A = new ArrayBuffer[Array[(Long, Array[Double], Array[Double], Double, Boolean)]] I would like to do same in chisel. In chisel I know one way of…
Foutse
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How to use "hierarchical path" of chisel/scala?

In verilog there is such a way to access other module's stuff, as I know it was called "hierarchical path", here is a verilog RTL module A; reg a; endmodule module tb; A u_A(); wire b; assign b = u_A.a; // hierarchical path endmodule Could…
Lin Frank
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difference with vvadd and mt-vvadd in riscv benchmarks

In the riscv-test, specifically the benchmarks test. What is the difference between the vvadd and mt-vvadd test??? Both say "This benchmark adds two vectors and writes the results to a third vector. The input data (and reference data) should be…
mem
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Chisel: How to model a variable incremented in a unrolled loop

Let's say I have a Vec of Bool. I want to fill a new Vec of the same size with values equal to a number of true values I've seen up to this index in the original Vec. I want to do it combinationally. With my HLS background and coding style settled…
aayupov
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Chisel3: Bitwise negation operator

There appears to be either a bug with or undocumented changes to the bitwise negation operator between chisel2 and chisel3. Chisel3 code not working import chisel3._ class bitwise_neg extends Module { val io = new Bundle { val in =…
plenn08
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Chisel3 disable GEN wires

I want to leave some ports unconnected, but all unconnected ports connects to GEN registers like: wire instance1_io_somePort; reg _GEN_3; // Want disable generation of this my_module instance1( ... …
SpaceCowboy max
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Controlling the VCS command line when using PeekPokeTester

Is there a way to specify options to VCS when using the PeekPokeTester? In particular, I would like to: 1) Enable System Verilog for black box code 2) Control the macro defines to disable the random number-based initialization. (I want to see…
Steve Burns
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Speed up sbt in China when using Chisel

All I a new users of Chisel in China and I found Chisel is build its program by using sbt. However, sbt seem need to download a lot of thing before it get to work. Do anyone have any idea to speed up this? Thank you.
Jimmy Stone
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How to add 3 number together?

There are 3 Uint 8 bits numbers. I want to sum up these numbers. How to describe it in chisel? s = a + b + c // s is 10 bits number If the only way to describe it as following, what's the benefits compare to traditional HDL? s0 = a + b // s0 is 9…
BBKing
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Error reported while running Laucher by chisel

I downloaded the chisel-tutorial which is offered on the website of usb-bar. In order to do practise I created a scala file named as "Regfile.scala" under the path: "chisel-tutorial/src/main/scala/solutions/Regfile.scala". The Test-file is stored…
Lishan Zhang
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Test multiple decoupled input ports using OrderedDecoupledHWIOTester

Does OrderedDecoupledHWIOTester support testing a DUT that has two or more decoupled input ports? For example, is there any way to express something like: inputEvent(decoupledPort1.bits <- 10) inputEvent(decoupledPort2.bits <- 11) to create two…
P. Meng
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Chisel AlreadyBoundException

I am developing a simple on chip memory for an SoC, based on Sodor scratchpad memory. So, first I'm converting a slightly modified version of that design to chisel 3. Now, I'm getting this exception regarding a bounded type that I can't…
isururathnayaka
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Initialize class depending on config value

I would like to find out how it is possible to initialize a Module, depending on a value. So I have a config.extend value which will decide if the core will instantiate of the Core or ExtendedCore module. However I am getting the error "value := is…
Mrchacha
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How to retrieve Rocket Core module parameters from Top module in fpga-zynq repository

My goal is to add counters to the rocket class of the Rocket Core module of the fpga-zynq repository. I want to count parameters like ctrl_stalld, id_stall_fpu ... while the chip is running on a FPGA. I successfully generated Verilog code and a…
mtosch
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