Chisel3 disable GEN wires

Question

~~I want to leave some ports unconnected, but all unconnected ports connects to GEN registers like:~~

wire instance1_io_somePort;
reg _GEN_3;                 // Want disable generation of this

my_module instance1(
  ...
  .some_port(instance1_io_somePort)
)

assign instance1_io__somePort = _GEN_3; // and this strings.

Is it possible in chisel3 to disable any assignments to _GEN_X registers?

================update_14_07_17================

Question not about io ports, its about internal GEN signals Example below

import chisel3._

class A extends Bundle {
  val in = Input(Bool())
  val out = Output(Bool())
}

class X extends Module {
  val io = IO(new Bundle {
    val A_IF = new A
  })
  val reg = RegInit(UInt(2.W), init = 0.U)


  io.A_IF.out := (reg === 2.U)

  when(io.A_IF.in === true.B){
    reg := 1.U
  }.elsewhen(io.A_IF.in === false.B){
    reg := 2.U
  }
}

object example extends App {
  Driver.execute(Array("-td", "./"), () => new X())
}

This chisel code generates bunch of verilog

module X(
  input   clock,
  input   reset,
  input   io_A_IF_in,
  output  io_A_IF_out
);
  reg [1:0] reg$;
  reg [31:0] _GEN_2; // don't wanna this reg to appear
  wire  _T_7;
  wire [1:0] _GEN_0; // and this 
  wire  _T_12;
  wire  _T_15;
  wire [1:0] _GEN_1; // and this wires 
  assign io_A_IF_out = _T_7;
  assign _T_7 = reg$ == 2'h2;
  assign _GEN_0 = io_A_IF_in ? 2'h1 : reg$;
  assign _T_12 = io_A_IF_in == 1'h0;
  assign _T_15 = _T_12 & _T_12;
  assign _GEN_1 = _T_15 ? 2'h2 : _GEN_0;
`ifdef RANDOMIZE
  //chisels randomize code here
`endif
  always @(posedge clock) begin
    if (reset) begin
      reg$ <= 2'h0;
    end else begin
      if (_T_15) begin
        reg$ <= 2'h2;
      end else begin
        if (io_A_IF_in) begin
          reg$ <= 2'h1;
        end
      end
    end
  end
endmodule

I want to know, is it possible to disable generation of _GEN_2 and _GEN_1 wires and _GEN_0 reg? Why this gens is appeared?

Can you share a little bit more about what you're trying to do? Chisel3 is moving away from unconnected wires, ports, and registers so I want to better understand your use case. — Jack Koenig, Jul 13 '17 at 20:23
Thanks for response! Added simple chisel example code in question. My first example was not correct enough. — SpaceCowboy max, Jul 14 '17 at 11:59

score 2 · Accepted Answer · answered Jul 19 '17 at 00:38

_GEN is the prefix for intermediate nodes generated by Firrtl, the IR and compiler for Chisel3.

These intermediate nodes are necessary because Firrtl can only emit a single Verilog op per line. This restriction is due to the often tricky width semantics of Verilog--It is much safer to avoid these kinds of subtle issues altogether.

Chisel3 disable GEN wires

1 Answers1