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Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

Features

  • Hardware construction language (not C to Gates)
  • Embedded in the Scala programming language
  • Algebraic construction and wiring
  • Abstract data types and interfaces
  • Bulk connections
  • Hierarchical + object oriented + functional construction
  • Highly parameterizable using meta-programming in Scala
  • Supports layering of domain specific languages
  • Sizable standard library including floating-point units
  • Multiple clock domains
  • Generates low-level Verilog designed to pass on to standard ASIC or FPGA tools
  • Open source on GitHub with modified BSD license
  • Complete set of docs
  • Growing community of adopters

Resources

680 questions
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Dynamic test harness in chisel 3

We are implementing a processor in Chisel and have many very tricky test cases. For elements that have a lot of state, we want to generate long sequences of test vectors on the fly, and calculate the correct response on the fly as well. In Chisel…
seanhalle
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How to make Chisel generate flip flops with enable?

We are implementing a processor pipeline, and want an efficient way to stall it. If we had control over the circuit, then we would use latches that have an enable input. To stall, just disable the latches, and then they won't update on the next…
seanhalle
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How to initialize ShiftRegister primitive in Chisel

We are using ShiftRegister in Chisel 2 to implement a delay. But it's not clear how to force it to initialize to a value of our choosing, such as forcing it to zero (NOT random). How to do this?
seanhalle
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Incorrect syntax of Chisel

I am learning chisel3. I want to run the code in order to see the result. Here is my code. I command "sbt run" and show these errors. It seems that I use ".W" to define width is illegal in Chisel,but the user guide obviously tells me that it's…
jjlin
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Compiling chisel source files in chisel project template

I'm new to chisel. Currently I'm following chisel-tutorial wiki using chisel3. After cloning the chisel project template linked there, I tried to test and generate verilog output from GCD.scala source file. I got the following error. > run…
isururathnayaka
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Generating verilog for riscv-sodor

I'm working on riscv-sodor and I want to modify the Makefile to generate Verilog. How can I do this task? Regards,
FadrixMH
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Sodor Processor Collection. Eclipse Setup

I'm trying to setup the Sodor Processor Collection (RISC-V) from Github. My main goal is to setup the 1-Stage Processor in my own chisel project in order to modify it and possibly write a scala testbench. Currently i'm doing the following: Cloning…
mtosch
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Chisel installation error

While following the tutorial on the Chisel official website for installation, I came to the point where I should test if the installation was done correctly. Doing so yields this error: set -e -o pipefail; "sbt" -Dsbt.log.noformat=true…
Ammar Kurd
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How to build a Zscale core? (RISC-V, rocket-chip)

I am referring to the following link, https://github.com/ucb-bar/zscale/issues/1 which denotes that zscale can be built from the rocket-chip generator with just different build option. make CONFIG=ZscaleConfig MODEL=ZscaleTop verilog"…
joist
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Chisel HDL for CPLDs

Is it possible to use the Chisel HDL with a CPLD? If yes, have you tried it, could you share experience please?
Cap
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Cannot use Bool in class parametrization to reverse reset polarity

I just started out with Chisel and wrote a simple counter to blink an led. The FPGA board (Lattice iCEstick) has an inverted reset signal, and instead of changing the polarity in the generated verilog, I want to set it in Chisel. I found that Module…
Oguz Meteer
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Partial write enable register bits

I am trying to build a 64-bit register, wherein the write-enable signal can be configured for every flip flop separately. Using the RegEnable object, var test = RegEnable(UInt(5),Bool(true)) test(UInt(0),Bool(false)) the register can be…
Arjun
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Chisel.TestApplicationException: test application exit - exit code 139

I got the above Chisel crash and I don't know what it means. Any ideas? The circumstances are that I'm trying to increase the size of my designed memory system from 512KB to 1MB. The 512KB version tests good. Twice as many banks in the 1MB…
Mykland
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java.utilNoSuchElementException: None.get for Vec

Perhaps I'm going about something the wrong way. I have a number of buffers that need to get locked and unlocked as part of the behavior of a state machine. I thought it would be perfect to use a Vec of Reg to store the state from clock to clock…
Mykland
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Recommended Java/Scala settings for Chisel

Recently, I've been learning Chisel from the top down, having had no previous exposure to Scala and only passing exposure to Java. As I have attempted larger and larger hardware constructs, I'm starting to generate cryptic errors from Java that…
Mykland
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