Case statement in verilog

Question

I came across priority encoder design and found out a new way to do it using a case statement. The only thing that is confusing is, does a case statement give priority to cases? Example:

case(1'b1)                                
  A[3]: Y<=4'b1000;             
  A[2]: Y<=4'b0100;  
  A[1]: Y<=4'b0010;  
  A[0]: Y<=4'b0001;  
  default:Y<=4'b0000;
endcase

Here if I give A as 1111 Y gets 1000 i.e it gives priority to the first case statement. Why is this so?

Morgan · Answer 1 · 2013-03-14T20:18:29.697

I would refactor this to :

casez(A)                                
  4'b1???: Y<=4'b1000;             
  4'b01??: Y<=4'b0100;  
  4'b001?: Y<=4'b0010;  
  4'b0001: Y<=4'b0001;  
  default: Y<=4'b0000;
endcase

Then there is no need to worry about priority, each match is unique.

From IEEE Std 1800-2009 (IEEE STANDARD FOR SYSTEMVERILOG)

12.5.2 Constant expression in case statement
A constant expression can be used for the case_expression. The value of the constant expression shall be compared against the case_item_expressions.

The following example demonstrates the usage by modeling a 3-bit priority encoder:

logic [2:0] encode ;

case (1)
  encode[2] : $display("Select Line 2") ;
  encode[1] : $display("Select Line 1") ;
  encode[0] : $display("Select Line 0") ;
  default $display("Error: One of the bits expected ON");
endcase

12.5.3 unique-case, unique0-case, and priority-case
The case, casez, and casex keywords can be qualified by priority, unique, or unique0 keywords to perform certain violation checks. These are collectively referred to as a priority-case, unique-case or unique0-case. A priority-case shall act on the first match only. Unique-case and unique0-case assert that there are no overlapping case_items and hence that it is safe for the case_items to be evaluated in parallel.

...

priority casez(a) // values 4,5,6,7 cause a violation report 
  3’b00?: $display("0 or 1");
  3’b0??: $display("2 or 3");
endcase

I am not sure how well supported the priority case statements are supported by synthesis tools though.

Full SystemVerilog Standard (2012) here: https://standards.ieee.org/findstds/standard/1800-2012.html — Brian Carlton, Feb 25 '17 at 02:17
`Then there is no need to worry about priority, each match is unique.` Why? Would a synthesis tool infer this correctly? — Jean, Aug 18 '20 at 01:42
@Jean "keywords to perform certain violation checks" They are intended for the designer to imply intent, and have a formal check they have not made a mistake in their code. I think your last question is why would a synthesis tool infer incorrectly? I had no experience of using these with synthesis so added a disclaimer *I did not know*. My point was not about the correctness of generated code but about the compatibility of these new keywords, as synthesis tools have often been behind on implementing the new features of language. There is also no standard that a synthesis tool must support. — Morgan, Aug 19 '20 at 08:52

score 7 · Accepted Answer · answered Mar 14 '13 at 20:15

7

Yes, there is a priority, based off of the order. According to the Verilog-2001 spec, section 9.5:

The case item expressions shall be evaluated and compared in the exact order in which they are given. During the linear search, if one of the case item expressions matches the case expression given in parentheses, then the statement associated with that case item shall be executed.

answered Mar 14 '13 at 20:15

dwikle

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Ohh. I have a doubt then. Isn't this similar to writing an if else statement? Then why to write a case statement? – aditya3524 Mar 14 '13 at 20:24
2

@aditya3524 case statement is cleaner, and generally preferred over if else chains. – Morgan Mar 14 '13 at 20:27
1

Personally I've rarely seen a priority encoder written this way. It should be equivalent to a bunch of if/else statements. This is more compact but I find it tricky to read since the value inside case(...) is a constant. – dwikle Mar 14 '13 at 20:29
In terms of hardware, if-else will generate muxes but case should be combinational gates.I will check what hardware I am getting by writing the case statement in this way.. – aditya3524 Mar 14 '13 at 20:34
1

@aditya3524 If the two styles of syntax are logically equivalent, synthesis should give you the same hardware. Synthesis should give you the smallest possible implementation that meets the timing requirements. – Morgan Mar 15 '13 at 21:29

Case statement in verilog

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