Bit width different in verilog

Question

What is different between {a + b} and (a + b) in verilog. I used the simulation to do:

reg [3:0] a = 4'b0001;
reg [3:0] b = 4'b1111;
reg [4:0] c = (a + b); give the result c = 5'b1_0000

but

reg [4:0] c = {a + b}; give c = 5'b0_0000;

It means the (a + b) can give the result 5 bits, but {a + b} give 4 bits. I don't know why. Please help me.

Thank you

I think the question is why is the output different if the concatenation operator is used. This is by no means an answer, but I think that the fact that a and b are both 4 bits wide is part of the issue relative to the concat operator being used. It might be worth while to prove that letting a and b become 5 bits wide get the expected behavior. At that point I think it comes down to how the concatenation operator slices the result width. — Rich Maes, Sep 16 '16 at 15:57
I don't know but with the concatenation the result will be 4 bits, I used this to assign to the 4 bit signal. — Thang Nguyen Toan, Sep 16 '16 at 16:05
IEEE Std 1364-2005 5.4 Expression bit lengths, IEEE Std 1800-2012 11.6 Expression bit lengths. (a+b) is a context determined bit length while {a+b} is a self determined bit length using the max(L(a), L(b). — , Sep 16 '16 at 18:21

score 3 · Answer 1 · answered Sep 16 '16 at 20:04

Each expression in a concatenation is self-determined. {expr1,expr2, ...}. In your example, there is just one expression, and it happens to be a + b. According to Section 11.6 Expression bit lengths in the IEEE 1800-2012 LRM , L(a+b) in a self-determined context is Max(L(a),L(b)), which is 4 bits. Otherwise it is 5 bits in a context of an assignment.

Bit width different in verilog

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