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Questions tagged [alu]

ALU stands for Arithmetic Logic Unit, that performs arithmetic and logical operations for computer systems.

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Best way to distinguish signed and unsigned integers in ALU?

I'm developing my own virtual 4-bit ALU. I'd like to create calculator (+, -, *, /, %, only integers, maybe more bits). My target is to understand it thoroughly, not to build an efficient device. Currently I've implemented 4 functions: Adding.…
Mark Miller
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Designing ALU Control block for single cycle MIPS

Hope this isn't off topic for Stack Overflow. I was learning about MIPS and I've gotten stuck at this step. This is the truth table for the ALU Control Block. Now this is the first time I'm coming across such a complicated truth table with don't…
user1265125
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Z80 flags - how to generate?

I'm designing a Z80 compatible project. I'm up to designing the flags register. I originally thought that the flags were generated straight from the ALU depending on the inputs and type of ALU operation. But after looking at the instructions and the…
user1530335
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Concise expression for the x86 overflow flag?

I need a concise way to express the x86 Overflow Flag as a function of the two operands. I understand that the core sets OF when both operands have the same sign but the result has a different sign. For example, ADD SRC[31..0], DEST[31..0] Can OF…
srking
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ALU-n Procedure in Scheme

I'm a beginner to the Scheme language, so I'm having trouble writing a procedure to take in an n-bit number and put it into an ALU. The ALU is supposed to be constructed using 1-bit ALU's. Here is the 1-bit ALU: (define ALU1 (lambda (sel a b…
aclark
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I can't get the addition and subtraction to execute correctly and the results I'm getting are wrog. How can I fix this?

So I'm trying to desgin a Processor for a university project and as I was going back to check my code I found out that my ALU unit doens't produce the correct results for addition and subtraction. Can you help me solve this? My code is as…
DilligentSlacker
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How can I convert 4 bit std vector to 5 bit vector in VHDL?

I am stuck in converting my 4 bit std vector to 5 bit. I am supposed to do logic operations and arithmetic operations with 4 bit inputs. (4 bit ALU) However, for arithmetic operations, I might have a carry out bit and I don't know how to keep it.…
HARUN SASMAZ
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An ALU in Verilog, lack of output while simulating

I write an simple ALU in verilog like this: input [15:0] in; output reg [15:0] out; reg [15:0] r [0:7]; reg [3:0] opcode; reg [3:0] outreg; reg [3:0] var1, var2; reg [15:0] a1, a2; parameter STO = 4'b0000; parameter ADD = 4'b0001; parameter MUL =…
Zh.Z
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VHDL 32 bit ALU code

I need to create a 32 bits ALU, with alu function, and adder/Sub, shifter, and comparator. when alu function is 0001, it goes to adder, when alu function is 0010, it goes to sub, when alu function is 1001, it goes to logical shifter left b-alu…
N.chen
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Store Word and ALU in assembly

I have a question about the Store Word function in assembly. I know that the store word writes values to memory locations. But the question in my assignment asks me what the ALU does during these SW operations. When I simulated it first we add a 0…
Hazin C.
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I need a flowchart that describes these 32-adder Multiplication Hardware

I'm looking for a flowchart explanation of how both of these 32-adder Multiplication hardware pieces work: The other: An example of how the flowchart could describe the hardware is seen here: I'd honestly just like the flowchart so I have a…
Dan
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Verilog Arithmetic Equation System Exercise

I am new to Verilog and I found some interesting exercises to work on but there is this one exercise I am stuck on, can anyone help me ??? The exercise: Implement an arithmetic equation system which, when given some values at its inputs, will give…
Techflow
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Verilog: ALU gives wrong output

I'm studying Verilog and here's my first ALU. I can't understand why the output does not display in the tester block. Sample outputs(scroll horizontally): FAIL: a=00010010000101010011010100100100, b=11000000100010010101111010000001, op=101, …
user2963044
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Hardware Multiplication ALU

I have multiplicand 5 , multiplier 7 which they are binary representation : 5 = 0101 , 7 = 0111 (4-bit) Register A to save the data to be multiplied(Multiplicand). Register B to save the multiplier data (Multiplier). Register P to save…
0x00b0
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Procedural assignment to a non-register shiftedy is not permitted, left-hand side should be reg/integer/time/genvar -- this is the error I am getting

I have almost solved this question and made changes in the code as shown below. I am also not getting any error but the only thing is that the output of 'shiftedy' is not as expected. Also, I use Xilinx to run my projects and I am getting red line…
Palak Halvadia
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