VHDL 32 bit ALU code

Question

I need to create a 32 bits ALU, with alu function, and adder/Sub, shifter, and comparator. when alu function is 0001, it goes to adder, when alu function is 0010, it goes to sub, when alu function is 1001, it goes to logical shifter left b-alu bits, when alu function is 1010, it goes to logical shifter right b-alu bits and so on.

I already have 32 bit adder/sub and 32 bits shifter code.

package c31L_pack is

library ieee;
use ieee.std_logic_1164.all;

package c31L_pack is
constant ZERO          : std_logic_vector(31 downto 0) :=
  "00000000000000000000000000000000";
constant ONES          : std_logic_vector(31 downto 0) :=
  "11111111111111111111111111111111";


constant BW : integer:=32;
constant SEL3   : integer:=3;
constant SEL1   : integer:=1;
constant OP : integer:=16;
constant reg_field: integer:=6;
constant immediate_size: integer:=15;


subtype alu_function_type is std_logic_vector(3 downto 0);

constant alu_nop                        : alu_function_type := "0000";
constant alu_add                        : alu_function_type := "0001";
constant alu_sub                        : alu_function_type := "0010";
constant alu_comp                       : alu_function_type := "0011";
constant alu_slt                            : alu_function_type := "0100";
constant alu_and                        : alu_function_type := "0101";
constant alu_or                             : alu_function_type := "0110";
constant alu_not                        : alu_function_type := "0111";
constant alu_xor                        : alu_function_type := "1000";
constant alu_shift_logic_left       : alu_function_type := "1001";
constant alu_shift_logic_right      : alu_function_type := "1010";
constant alu_shift_arith_left       : alu_function_type := "1011";
constant alu_shift_arith_right      : alu_function_type := "1100";
constant alu_mov       : alu_function_type := "1101";

type mux_in_16 is array((OP-1) downto 0) of std_logic_vector(BW-1 downto 0);
type mux_in_2 is array(1 downto 0) of std_logic_vector(BW-1 downto 0);
end;

1 bits:

library ieee;
use ieee.std_logic_1164.all;
entity adder1 is
port(a         : in  std_logic;
     b         : in  std_logic;
     cin       : in  std_logic;
     sum_def    : out std_logic;
     carry_borrow   : out std_logic);
end; 

architecture logic of adder1 is

begin

process(a,b,cin)

begin

sum_def <=a xor b xor cin;
carry_borrow<=(a and b) or (a and cin) or (b and cin);

end process;
end architecture; --architecture logic

and 32 bits adder/sub

library ieee;
use ieee.std_logic_1164.all;
use work.c31L_pack.all;

entity adder32 is
port(a3_32    : in  std_logic_vector(BW-1 downto 0);
    b3_32    : in  std_logic_vector(BW-1 downto 0);
      cin   : in std_logic;
      sub   : in std_logic;

      sum_32    : out std_logic_vector(BW-1 downto 0);
      cout  : inout std_logic;
      ov    : out std_logic);
end; 

architecture logic of adder32 is

component adder1
port(a         : in  std_logic;
  b         : in  std_logic;
  cin       : in  std_logic;

    sum_def : out std_logic;
    carry_borrow    : out std_logic);
end component;

for add1: adder1 use entity work.adder1(logic);

signal carry_i :std_logic_vector(BW-2 downto 0):=(others=>'0');
signal xor_out :std_logic_vector(BW-1 downto 0):=(others=>'0');
signal oz :std_logic;

begin


Exclusive_or:for i in  BW-1 downto 0 generate
begin
xor_out(i)<=b3_32(i) xor sub after 19ns;
end generate;


add1: adder1 port    map(a=>a3_32(0),b=>xor_out(0),cin=>sub,sum_def=>sum_32(0),carry_borrow=>carry_i(0));   
add_2_31 : for i in 1 to BW-2 generate
     add1 :adder1 port map(a=>a3_32(i),b=>xor_out(i),cin=>carry_i(i-1),sum_def=>sum_32(i),carry_borrow=>carry_i(i)); 
end generate;
add32: adder1 port map(a=>a3_32(BW-1),b=>xor_out(BW-1),cin=>carry_i(BW-2),sum_def=>sum_32(BW-1),carry_borrow=>cout);        

oz<=carry_i(BW-2) xor cout after 19 ns;
with oz select
ov <= 'Z' when "1",
    '0' when "0";
end architecture; --architecture logic

I am trying to get every result after that find out output using the function code, I got a lot of error,I try to find the way to solve that. What should I do? Thanks for all your help. I just want to get the add and sub first, so that I know what should I do.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.c31L_pack.all;

ENTITY alu32 IS
GENERIC (BW : INTEGER :=32);
PORT ( a_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
     b_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
     alu_op : in alu_function_type ;
     g : out STD_LOGIC ;
     e : out STD_LOGIC ;
     l : out STD_LOGIC ;
     o_alu32 : out STD_LOGIC_VECTOR (BW -1 downto 0);
     c_alu32 : inout STD_LOGIC ;
     ov_alu32 : out STD_LOGIC );
end alu32;

architecture Behavioral of alu_32 is

component adder32 
port(a3_32    : in  std_logic_vector(BW-1 downto 0);-<std_logic_vector> is not declared.
 b3_32    : in  std_logic_vector(BW-1 downto 0);-<std_logic_vector> is not declared.
  cin   : in std_logic;-<std_logic> is not declared.
  sub   : in std_logic;-<std_logic> is not declared.

  sum_32    : out std_logic_vector(BW-1 downto 0);
  cout  : inout std_logic;
  ov    : out std_logic);
  end component;

signal o1:std_logic_vector(BW-1 downto 0);
signal c1:std_logic;
signal ov1:std_logic;
signal o2:std_logic_vector(BW-1 downto 0);
signal c2:std_logic;
signal ov2:std_logic;

begin
adder32 port map(a3_32=>a_alu32,b3_32=>b_alu32,cin=>"0",sub=>"1",sum_32=>o1,cout=>c1,ov=>ov1);
adder32 port map(a3_32=>a_alu32,b3_32=>b_alu32,cin=>"0",sub=>"0",sum_32=>o2,cout=>c2,ov=>ov2);

end Behavioral;

error massage: ERROR:HDLCompiler:374 Line 37: Entity is not yet compiled.

ERROR:HDLCompiler:69 Line 40: is not declared.

ERROR:HDLCompiler:69 Line 41: is not declared.

ERROR:HDLCompiler:69 Line 42: is not declared.

ERROR:HDLCompiler:69 Line 43: is not declared.

ERROR:HDLCompiler:69 Line 45: is not declared.

ERROR:HDLCompiler:69 Line 46: is not declared.

ERROR:HDLCompiler:69 Line 47: is not declared.

ERROR:HDLCompiler:69 Line 50: is not declared.

ERROR:HDLCompiler:69 Line 51: is not declared.

ERROR:HDLCompiler:69 Line 52: is not declared.

ERROR:HDLCompiler:69 Line 53: is not declared.

ERROR:HDLCompiler:69 Line 54: is not declared.

ERROR:HDLCompiler:69 Line 55: is not declared.

ERROR:HDLCompiler:806 Line 58: Syntax error near "port".

ERROR:HDLCompiler:806 Line 59: Syntax error near ";".

Your code doesn't analyze as provided. The selected signal assignment is missing an others choice or should be conditioned `with To_Bit(oz) select ov <= 'Z' when '1', '0' when '0';` or a conditional signal assignment. Note the '1' and '0' instead of "1" and "0". The 'Z' stands for high impedance. Code review questions should be submitted to [Code Review Stack Exchange](https://codereview.stackexchange.com/questions/tagged/vhdl) (tagged vhdl). What is producing and what should the result be? And despite Modelsim allowing it a space is required - 19ns violates syntax rules, use 19 ns. — , Mar 09 '16 at 20:49
Subtracting b from a uses the two's complement of b (not b and invert the LSB carry in). Comparison can require two outputs (equal and greater than, equal and less than or greater than and less than). You haven't shown anything that demonstrates shifting for which you'd select between the adder output and the shift result based on operation. Show the complete set of operations. — , Mar 09 '16 at 20:52
@user1155120 The current code is not working and therefore off-topic at Code Review. However, once it works OP is more than welcome to come over and drop his code for examination. VHDL isn't a popular tag there, so make sure the question is above average or it won't attract much attention. — Mast, Mar 09 '16 at 20:55
Package c31L_pack is missing, (BW, alu_function_type) concurrent statements (generates) don't go in waveforms on selected signal assignment statements. The adder32 actually looks functional. The architecture body of alu_32 is completely wrong. You only need one adder, steer it's inputs with a case statement or selected signal assignment, inverting b and carry in for subtract. Also see [32-bit comparator waveform issue (VHDL)](https://stackoverflow.com/questions/35530475/32-bit-comparator-waveform-issue-vhdl/35531002). — , Mar 09 '16 at 23:11
Your posted error messages are useless, because you didn't specified in which posted code block they occur. To implement the ALU, you should draw a block diagram of it **first**. This will include all sub-components, an output multiplexer, and the connections in between. **Then** code it in VHDL. — Martin Zabel, Mar 10 '16 at 07:25

score 0 · Answer 1 · answered Mar 09 '16 at 18:51

An ALU, by definition, has two data inputs: a and b, a function code input, and a status output as well as the result output. This would lead to an entity definition like

entity alu is
generic
(
    width      : integer
);
port
(
    a          : in std_logic_vector(width - 1 downto 0);
    b          : in std_logic_vector(width - 1 downto 0);
    fc         : in fc_t;
    status     : out sc_t;
    result     : out std_logic_vector(width downto 0)
);

(which looks quite different to yours).

Additional to that, you'll need two enumerated types to encode status and function code:

type fc_t is (fc_add, fc_add, fc_shift, fc_compare);
type sc_t is (sc_ne, sc_eq, sc_err);

I'll leave the architecture to you (you already have most of it, you just need to put it to the right place).

VHDL 32 bit ALU code

1 Answers1