Out of the first two diagrams, only the first seems to be partially correct. I've seen the second diagram in Computer-Organization-Design, and for me it is not correct as well (or atleast I can't decipher that :-)).
So let me try to explain only the first diagram
Mcand = Multiplicand register
Mplier0 = 0th bit of the Multiplier register (lsb)
Mplier1 = 1st bit of the Multiplier register
Mplier31 = 31st bit of the Multiplier register (msb)
Mcand.Mplier1 is performing logical "AND" operation Multiplicand and Multiplier first bit. e.g. if Mcand is 1101 and Mplier1 is 1 the result is 1101, and if Mplier1 is 0, the result is 0000
Now the top-right most ALU has two inputs
- Left input: Mcand.Mplier1 a 32 bit value, as explained above.
- Right input's 32 bit value is made by, 31st bit is zero as shown. And rest of the 30 bits are most signficant bits of Mcand.Mplier0 except the 0th bit. 0th bit goes directly to set Product0 bit (i.e. 0th bit of the Product register)
Now the ALU at the second layer (or row), has two inputs as well.
- Left input: Mcand.Mplier2 a 32 bit value, as explained above.
- Right input's 31st bit has to be the "carry out" of the first ALU, the diagram sets it to zero, which seems to be incorrect. Rest of the 31 bits are set from most significant 31 bits of the output of first ALU. The remaining 0th bit output of first ALU goes directly to set Product1 bit.
This is repeated for the remaining 30 ALUs.