ALU stands for Arithmetic Logic Unit, that performs arithmetic and logical operations for computer systems.
Questions tagged [alu]
188 questions
3
votes
2 answers
getting error for VHDL shift_left operation
I have been searching this for a while and have not been able to replicate any posted solutions online so I was hoping some of you wonderful people could help me out.
I am creating an ALU. i have a two 32 bit inputs and one 32 bit output along…
Zannith
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3
votes
1 answer
Does each Floating point operation take the same time?
I believe integer addition or subtraction always take the same time no matter how big the operands are. Time needed for ALU output to be stabilized may vary over input operands, but CPU component that exploits ALU output will wait sufficiently long…
codebomb
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3
votes
2 answers
Continuous assignment verilog
-This code is written in verilog using Modelsim 10.2d.The errors below indicate there is some problem with {cout,l3} assignment.
module alu(a,b,bin,cin,op,cout,res);
input [31:0] a,b;
input [1:0] op;
input bin,cin;
reg [31:0] l1,l2,l3;
output…
user3409814
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3
votes
3 answers
Can Registers inside a CPU do Arithmetics
I read in many detailed articles that Data from the Registers are used as Operands for the ALU to add two 32-bit integers, and this is only one small part of what the ALU can actually do.
However I also read the Register can even do arithmetic too?…
user3129884
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- 3
2
votes
2 answers
Trouble implementing unsigned component to conditions of ALU in VHDL
I have to create an ALU that has conditions for add, add unsigned, sub, sub unsigned, and, or, xor, nor, slt, and slt unsigned. I am having difficulty implementing the design to include the unsigned conditions. I have noted in the code where the…
Fabian
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2
votes
1 answer
ALU hdl produces wrong values
(nand2tetris course)
Expected result:
| x | y |zx |nx |zy |ny | f |no | out |
| 0000000000000000 | 1111111111111111 | 1 | 1 | 1 | 1 | 1 | 1 | 0000000000000001 |
My HDL code's result:
| x | …
Sebastian Nielsen
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2
votes
0 answers
Proteus error:logic race conditions detected during transient analysis
I’m trying to design a simple alu that get two 5-bit number and return the result of adding them or subtract or multiply or divide.
With using ICs ,it goes well.However I want to design everything myself.
In designing divide I get error :
logic race…
Melika Z
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2
votes
2 answers
Verilog error: not a valid l-value
I'm trying to test if a wire(s) is on or not to signify if there is an error/overflow in my alu code. Given this code:
output reg[3:0]x; // line 149
output wire error;
output wire overflow;
always @* begin
if(error ||…
SasaS
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2
votes
1 answer
Logisim ALU Red Lines - Not Understanding Causes and How to Fix
I'm working on a project where I need to create my own CPU for a specific instruction subset of MIPS. I will admit I thought I understood the single-cycle datapath until this project. So excuse my confusion.
My issue is with my ALU. The ALU…
Pwrcdr87
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2
votes
2 answers
Unsigned multiplication in VHDL 4bit vector?
im making an ALU with an option to do A + 2B
but im having trouble getting my head around multiplying the 2B and getting the proper answer in my test bench.
EG: A = 0110 B = 0011
Equation is A + 2B
and im getting 0110
a snippit of my code…
lolbardsnin
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2
votes
1 answer
Why are ALU outputs undefined?
I am designing an ALU in Verilog while I am learning it. I came up with the following code:
Testbench:
module ALUtb;
reg clock = 1'b0;
reg [0:7] val1;
reg [0:7] val2;
initial begin
val1 = 8'b01010100;
val2 = 8'b10101000;
#50 $finish;
…
NigletDiglet
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2
votes
1 answer
Making a 16-bit ALU using 1-bit ALUs
Hello I am trying to create a 16-bit ALU from several 1-bit ALUs
I created a package named basic_alu1 which contains a component of the 1-bit ALU.The code for this is:
library ieee;
use ieee.std_logic_1164.all;
package basic_alu1 is
component alu1
…
user6345302
2
votes
1 answer
ALU with Structural VHDL?
I am trying to create an ALU using structural code in VHDL. The code was originally in Verilog and then I manually changed it all over to VHDL, so that's why I have many separate files...but in theory these should work. The following are the…
David C
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2
votes
2 answers
'sra' not working in VHDL
I am making a component which takes in input of 32 bits and a control input of 7 bits. What this component does is that it looks at last 2 bits of S and for
S = 00, it does logical shift left on inp
S = 01, it does logical shift right on inp
S =…
Ankit Shubham
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2
votes
2 answers
Input Output for 8-bit ALU using FPGA board
I am a newbie to xilinx so please excuse any stupidities in the code.
Ah so I am trying to design an 8-bit ALU and the module is working perfectly on the simulation but we need to take inputs and display outputs on FPGA board.
Technically I should…
Maira Muneer
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