How can I convert 4 bit std vector to 5 bit vector in VHDL?

Question

I am stuck in converting my 4 bit std vector to 5 bit. I am supposed to do logic operations and arithmetic operations with 4 bit inputs. (4 bit ALU) However, for arithmetic operations, I might have a carry out bit and I don't know how to keep it. Here is my code, I tried to define a temp 5-bit vector and make temp(4) to carry out.

    architecture Behavioral of alusmall is
    signal temp: std_logic_vector (4 downto 0);
    begin
    --.--Here we write which operations are launched according to M and S signals:
    temp <= (A and B) when (M='0' and S="00") else
    (A or B) when (M='0' and S="01") else
    (A xor B) when (M='0' and S="10") else
    (A xnor B) when (M='0' and S="11") else
std_logic_vector(unsigned(A) + unsigned(C1)) when (M='1' and S="00") else --.--now, the arithmetic part starts (M is one).
std_logic_vector(unsigned(A) + unsigned(B) + unsigned(C1)) when (M='1' and S="01") else
std_logic_vector(unsigned(A) + unsigned(not B) + unsigned(C1)) when (M='1' and S="10") else
std_logic_vector(unsigned(not A) + unsigned(B) + unsigned(C1));

How can I seperate temp(4) and temp(3 downto 0) in 4-to-1 multiplexer?

score 0 · Answer 1 · answered Nov 02 '18 at 08:50

Addition in VHDL does not automatically do bit-growth. To allow for a carry bit, simply append '0' to the MSB of the operands. (append the sign bit for signed arithmatic). This means you can simply take the resulting MSB as your carry bit.

eg.

op <= ('0' & A) + ('0' & B);
carry <= op(op'high);

numeric std also has a resize function to do this (for both signed and unsigned):

op <= resize(A, op'length) + resize(B, op'length)
carry <= op(op'high);

Another point - why not make your inputs and outputs unsigned, rather than SLV? then you wouldnt need all the type conversions (or you can use the numeric_std_unsigned library from VHDL 2008 to do arithmatic with std_logic_vector).

How can I convert 4 bit std vector to 5 bit vector in VHDL?

1 Answers1