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Questions tagged [alu]

ALU stands for Arithmetic Logic Unit, that performs arithmetic and logical operations for computer systems.

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How to concatenate 3 operation select bits in a 4-bit ALU design - VHDL

So I have been working on this assignment and it requires me to design a 4-bit ALU being controlled by a couple of bits(namely S1, S0, Cin/C0(carry in) and M) Depending on the value of M the ALU will perform either logical or Arithmetic operations.…
bzrk89
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verilog ripple alu .. got 'x' for slt operation

I'm trying to create a ripple alu from one bit alu, every thing is working fine except for the slt operation it's implemented like so, for the one bit alu there is input 'less' it's set to zero except for the LSB, it's got its vlaue from MSB of the…
Ehab AlBadawy
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Change VHDL testbench and 32bit-ALU with clock to one without

I wrote this VHDL-program vor an ALU and its testbench that is working: ALU-code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ALU_CLK is port( Clk : in std_logic; --clock signal InRegA,InRegB : in…
kimliv
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ARM without ALU how much for operations

I had a problem on ARM Cortex M3 with some functionality that requires multiply and divide natural numbers. The point is: if it's possible to make calculations between 128 bits numbers? I need to know how many assembly operations need software…
Mazeryt
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How do i connect my two modules?

I have to make a alu within a ralu that was 8 functions , but when I try to simulate the behavioral model for "ralu" all I get are X's (output) and Z's (input). What am I doing wrong? (When I simulate only the alu it works just fine) module alu( …
user3629371
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"Can't determine the definition of operator +" when designing a 16-bit ALU

I am designing a 16-bit ALU which does few operations. I have a syntax error: "Can't determine the definition of operator "+"". The following code does Signed & Unsigned addition and subtraction and shift operation. It does a few other operations…
user3053647
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How would I implement a 1-bit slt operation in an ALU? (MIPS)

This is a homework assignment, so I'm not looking for an answer, but guidance. The instructions say, "How would you implement a 1-bit slt operation in an ALU? Describe your solution using only AND, OR, and NOT. No need to diagram the logic gates,…
kcmallard
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Shifting left in 2's complement and multiplication

I'm implementing a simple (virtual) ALU and some other chips (adder, multiplier etc.). I'm using the 2's complement representation for my numbers. For multiplication of x and y, two 16-bit numbers, I thought I'd use left shifts along these lines…
Paz
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Type mismatch error in VHDL?

I'm designing a 1 bit ALU and using a structural approach. For some reason I keep getting a type mismatch error even though I'm only using std_logic_vectors for everything. I don't see what could be wrong? Here's the code: 1 bit ALU: LIBRARY ieee;…
user2929779
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How to handle carry out by using 1 bit ALU to create 4 bit alu in VHDL

I have to create a 1-bit ALU and then use that to create a 4-bit ALU. But I am having a lot of problems when handling the carry out. The 4-bit ALU can only have 2 selection lines and carry in it uses carry in order to generate 8 different cases.…
user3236694
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verilog doesn't see my function

module fa(a,b,cin,cout,sum); input a; input b; wire bxor; input cin; output cout; output sum; assign bxor = b ^ cin; assign sum = ((a^bxor)^(cin)); assign cout =…
El Cree
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nbit Bitslice ALU with For/IF Generate in VHDL

I'm designing a n-bit bitslice ALU with GENERATE and I wrote this code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY ALU IS GENERIC (n : integer := 8); PORT (A,B : IN std_logic_vector(n-1 DOWNTO 0); …
user1859201
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Assign instructions / algorithms to specific ALUs with CUDA / OpenCL?

I am pretty new to GPU programming. I read some material explaining the basic concepts. However, I want to know if it is possible to assign a set of instructions or a whole algorithm / binary to a specific ALU, such that I can be sure that these…
Richard Laurant
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Carry output issue during VHDL ALU synthesis

I'm trying to build and synthesize an ALU in VHDL but I get a problem as soon as I synthesize. I'd like my ALU to have a op-code for adding my two N-bits inputs and a carry that may be set by an input or by a sum that was calculated earlier. The…
Champiyann
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I have a few questions about ALU's....

So, I've been trying to learn about computers for the last few months and really learn in detail how they work. I was learning about subtractors recently and I was wondering.. First of all, to my understanding, a subtractor uses two's compliment to…
Julian Jefko
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