ALU stands for Arithmetic Logic Unit, that performs arithmetic and logical operations for computer systems.
Questions tagged [alu]
188 questions
2
votes
1 answer
Simple sum in IJVM
Suppose we need to make a sum of two binary numbers in ijvm, for example:
100 + 11 = 111
Translating all in ijvm:
ILOAD arg1 //100
ILOAD arg2 // 11
IADD
ISTORE i
Without making any changes to the code, what the content of the…
user4252099
2
votes
3 answers
How do I wire modules?
I have written all the code, including the modules, but I can't figure out how to wire the modules to the main program.
The ALU should be:
A (4bits) and B (4bits) as inputs, sel (3bits)
1st Module When sel = 000 => Add/ sel= 001 => Sub (A+B or…
L.L
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1 answer
McPAT: ALU per access power computation
I am working on McPAT. I wanted to know the formula they used in their power calculation of ALU and FPU.
In the logic.cc file, while initializing the ALU and FPU, they update a variable called per_access_energy. This variable is later used to…
Luniam
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1 answer
Is my VHDL 1-bit Behavioral ALU complete?
This is my first time writing VHDL code, and I'm wondering if this simple ALU VHDL code is complete. Everything I can find is for more complex ALUs, but I just need to write this simple one.
The problem is as follows:
Write a behavioral model that…
Drac
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2 answers
How does an Arithmetic Logic Unit do comparisons?
I am taking a course of system tools and architecture in my University and the first class is about how CPU and RAM talks and how CPU process the data. As explained by the Prof, CPU has an ALU (Arithmetic Logic unit) which performs arithmetic such…
eagertoLearn
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1 answer
When to break down VHDL?
Although I'm somewhat proficient in writing VHDL there's a relatively basic question I need answering: When to break down VHDL?
A basic example: Say I was designing an 8bit ALU in VHDL, I have several options for its VHDL implementation.
Simply…
Emphacy
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2 answers
32 Bit ALU in VHDL Carry Out
I'm supposed to write a simple 32 Bit Alu in VHDL. Everything is working fine, except for two things. The ALU is supposed to have an carry out and overflow flag and I cant't figure out how to implement that.
First a general question. The circuit…
DangerDan
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1 answer
VHDL : signal initialisation
I'm a beginner at VHDL and I have problems when to decide whether I should initialize my signal or not...
Here's an exemple :
entity tatoo is
port (
clk, reset : in std_logic;
opcode : in…
ZouZou
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2
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1 answer
How to design a simple Adder with separate carry and borrow flags?
I am implementing a simple adder. However, I have a need for a bit of a unique twist.
What I'm implementing is a "roll over" feature across a Code Segment(CS) register and an Instruction Pointer(IP) register. So, when you do a relative jump by +20,…
Earlz
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how does ALU work?
Implementing 8bit ALU in VHDL with unsigned numbers only. When the result of the sum is (1)00000000, 1 being the carry out, should the zero flag of the ALU be set to 1? Or the result is considered to be different from 0?
Andr
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How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would anyone be able to clarify what would be happening in it when it's executing an sll…
Ken Ely
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1
vote
1 answer
How exactly are AVX-512 instructions executed on ALU?
I have trouble understanding how 512 bit registers can be utilized on ALU on a single clock cycle. Are there multiple ALUs that divide the data or is there specialised ALU that can work with this?
Tapio Nevalainen
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What is the general purpose computer hardware for multiplication?
I am wondering what is the cost of multiplication operation in general purpose computers in terms of clock cycles. I mean what is the hardware or algorithm for multiplication. Is it Baugh-Wooley signed multiplication algorithm or Booth's algorithm…
Oguzhan
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1
vote
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ALU test bench using test vector file not working
I'm new to this, and the question might seem silly, but I've spent hours on this and the test bench just doesn't want to load the right values into the register before performing the arithmetic.
Here's what happens when I go to run the simulation
#…
Pete
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Flags for ALU in VHDL not updating when running simulation
So far everything works as intended except for the Cout (carryout) and V (overflow) when I simulate in the testbench. I get constant Us when performing addition and subtraction. I performed some of the calculations I'm testing by hand so I know…
user13042058