Questions tagged [nextpnr]

2 questions
3
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1 answer

How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles

I want to create a very compact parallel to serial shift register. I have manually designed a logic tile. I want yosys/nextpnr to just do the routing between this tile and the io pins. I have design the code to use yosys primitive, but nextpnr fails…
E. Timotei
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0
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1 answer

why are SB_LUT4 and SB_DFF not being packed by nextpnr?

I added the yosys tag, though this question is probably more about nextpnr (which has no tag on this site). I'm using yosys with nextpnr-ice40 on the following file. When I dump the design with --post-route /path/to/nextpnr/python/dump_design.py (I…
Hammdist
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