gate level parsing using yosys

Question

I want to parse the following sequential gate level net list. And I expect that the output will give me the gate ordering ( port order) so I can do other computation on the code. I tried to do that using yosys command read_verilog s27.v. I was able to debug the code, yet I could not get the cell library or any thing that will get me the gate ordering.

P.S: I tried that using abc compiler and I only got the primary inputs and outputs order not the gate, and I asked before if yosys can do that and I got positive feedbacks.

module s27 ( GND, VDD, CK, R, G0, G1, G17, G2, G3 );
  input  GND, VDD, CK, R, G0, G1, G2, G3;
  output G17;
  wire   G5, G10, G6, G7, G13, n1, n2, n3, n4, n5, n6, n7, n8, n9, n11,    
         n12,n13, n14;
  DFFSR \DFF_2/Q_reg  ( .D(G13), .CLK(CK), .R(R), .Q(G7) );
  DFFSR \DFF_0/Q_reg  ( .D(G10), .CLK(CK), .R(R), .Q(G5) );
  DFFSR \DFF_1/Q_reg  ( .D(n1), .CLK(CK), .R(R), .Q(G6) );
  INVX1 U1 ( .A(G17), .Y(n1) );
  INVX1 U2 ( .A(G2), .Y(n2) );
  INVX1 U3 ( .A(G3), .Y(n3) );
  INVX1 U4 ( .A(G6), .Y(n4) );
  AND2X1 U5 ( .A(n5), .B(n2), .Y(G13) );
  AND2X1 U6 ( .A(G0), .B(G17), .Y(G10) );
  OR2X1 U7 ( .A(n6), .B(n7), .Y(G17) );
  OR2X1 U8 ( .A(n14), .B(n8), .Y(n7) );
  AND2X1 U9 ( .A(n5), .B(n9), .Y(n8) );
  OR2X1 U10 ( .A(G1), .B(n12), .Y(n5) );
  AND2X1 U11 ( .A(n3), .B(n9), .Y(n6) );
  OR2X1 U12 ( .A(G0), .B(n4), .Y(n9) );
  INVX1 U13 ( .A(G7), .Y(n11) );
  INVX1 U14 ( .A(n11), .Y(n12) );
  INVX1 U15 ( .A(G5), .Y(n13) );
  INVX1 U16 ( .A(n13), .Y(n14) );
endmodule

Obviously the problem is not with parsing (yosys parses this code just fine). But it's not entirely clear to me what you would like yosys to do with this code. You want to determine the topological order of gates? That's easy: There is none! This netlist contains cycles: `./yosys -p 'hierarchy -generate * o:Y o:Q i:*; show' test.v` http://i.imgur.com/bg11Qqu.png — CliffordVienna, Nov 17 '15 at 13:50
@CliffordVienna Thank yo very much. Yes I want to determine the topological order of the gates not necessarily this verilog code , and write this order into separate text file. The second thing I want to ask you, can the hierarchy output ( netlists cycles) stored in text file or any other type data file ? Thanks a lot and appreciate the help — Never too late, Nov 17 '15 at 15:42
You can use the `tee` command to write the output of a command to a file: e.g. `tee -o hierarchy_out.txt hierarchy`. Not sure what this has to do with 'netlist cycles' thought.. If you want to get the cycles (aka strongly connected components): Use e.g. `scc -all_cell_types`. Right now there is no dedicated command to do topological sorting. If you'd describe a little bit what you are actually trying to do with the topological sorting, I'd consider writing a yosys command that prints that information. But only if I can be convinced that it is useful for something, of course.. — CliffordVienna, Nov 17 '15 at 15:58
I am working on extending privacy preserving verification tool [http://dl.acm.org/citation.cfm?id=2755829], that will ensure the privacy of both the IP owner and IP user. However, in this paper the combinational gates are only considered, not the sequential, and as you know in the sequential level the topological order is very important, so I need it to write the encryption code in each gate with the right order. I hope this is clear if not I can explain more, I really dont have to build a gate parser from scratch just to get the gate ordering, and yosys already do a great job in parsing — Never too late, Nov 17 '15 at 17:02
@CliffordVienna In addition to the comment above, I'd like to tell you that we used in the paper version the Veriwell simulator, it worked fine for the combinationel bench marks, because we didnt care about the order of evaluation, but since we need to extend it, we want to include the sequential where we have DFF's and lateches, and in that casde we need the topological order of the gates. Thanks a lot — Never too late, Nov 18 '15 at 05:45

score 3 · Accepted Answer · answered Nov 19 '15 at 14:42

3

The newly added torder command prints the cells in the design in topological order, if such an order exists. For example:

read_verilog test.v
hierarchy -generate * o:Y o:Q i:*
torder -stop DFFSR Q

This script applied to the code you posted produces the following output:

module s27
  cell U4
  cell U12
  cell U3
  cell U11
  cell U15
  cell U16
  cell U13
  cell U14
  cell U10
  cell U9
  cell U8
  cell U7
  cell U6
  cell DFF_0/Q_reg
  cell U1
  cell DFF_1/Q_reg
  cell U2
  cell U5
  cell DFF_2/Q_reg

Without the -stop option the command would also create dependencies for DFF output ports, which would result in loops. In such a case the command will print the loops and create a topological ordering for the remaining graph:

module s27
  loop DFF_2/Q_reg U10 U13 U14 U5
  loop DFF_0/Q_reg U15 U16 U6 U7 U8
  loop DFF_1/Q_reg U1 U11 U12 U4 U7
  cell U1
  cell DFF_1/Q_reg
  cell U4
  cell U12
  cell U3
  cell U11
  cell U15
  cell U16
  cell U2
  cell U5
  cell DFF_2/Q_reg
  cell U13
  cell U14
  cell U10
  cell U9
  cell U8
  cell U7
  cell U6
  cell DFF_0/Q_reg

I hope this helps.

answered Nov 19 '15 at 14:42

CliffordVienna

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This is exactly what we need, I implemented it and it worked perfectly. Thanks a lot.... – Never too late Nov 22 '15 at 11:38
Hello Mr.Clifforod, I just want to comment that the assign operation in not included in the torder command, and some of netlists contain it, can you help me in this regard. – Never too late Feb 16 '16 at 11:00
@Nevertoolate please open a new question with the Yosys tag. Make sure to include example verilog code, yosys script, and the output you get and how it differs from the output you want. – CliffordVienna Feb 16 '16 at 11:52
Is there any command that write the torder output to text file, I know that write_verilog will write the design output, but what about torder ???? – Never too late Mar 22 '16 at 14:58
Try "tee -o filename torder". – CliffordVienna Mar 22 '16 at 16:15

gate level parsing using yosys

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