How to map clock gate to tech library cell

Question

I have the following clock gate in the design:

module my_clkgate(clko, clki, ena);
  // Clock gating latch triggered on the rising clki edge
  input  clki;
  input  ena;
  output clko;
  parameter tdelay = 0;

  reg enabled;
  always @ (clki, ena) begin
    if (!clki) begin
      enabled = ena;
    end
  end

  assign #(tdelay) clko = enabled & clki;
endmodule

When synthesising with Yosys, the resulting netlist instantiates (for the reg enabled) a \$_DLATCH_P_ cell which is not included in the standard cell lib file I am using, even though the library does include latches.

Instead of trying to match enabled of this design to a standard latch cell from the library, I'd like to use the clock gate provided by the library instead that includes the AND gate, which has an interface like so:

module LIB_GATE (
  input CK,
  input E,
  output ECK);
endmodule

I already tried the following:

Simply replacing my_clkgate module source's contents with an instance to LIB_GATE and forwarding all port connections. Yosys complained that LIB_GATE is "not part of the design".
In addition to point 1, declaring LIB_GATE as an empty module (as shown above). This had the effect of leaving two empty modules, LIB_GATE and my_clkgate in the resulting netlist.
I also tried using the extract command with the library's Verilog models, unfortunately it fails to parse (I suspect the file contains some unsupported Verilog constructs such as specify blocks).

Of course, I could write a script that post-processes the netlist to replace my_clkgate with LIB_GATE instances, but I was wondering if Yosys can do that for me?

For reference, here is the "synth.ys" file that I am using:

read_liberty -lib  my_library.lib
script yosys_readfiles.ys
proc; opt; memory; opt; fsm -norecode; opt
techmap; opt
dfflibmap -liberty my_library.lib
abc -liberty my_library.lib
hilomap -hicell LIB_TIEHI Y -locell LIB_TIELO Y
clean
write_verilog -noattr -noexpr output.v
stat

Where the "yosys_readfiles.ys" is a file containing a read_verilog line with all the input files followed by a hierarchy -check -top my_design line.

I do not know about Yosis but on Design Compiler(Synopsys) there is a command `set_clock_gating_style` that allows you to chose the elements to use as clock gaters(and other options). Did you check for something similar in Yosis? — Krouitch, Jan 23 '17 at 15:55

score 1 · Accepted Answer · answered Jan 24 '17 at 10:16

In addition to the previous, declaring LIB_GATE as an empty module (as shown above). This had the effect of leaving two empty modules, LIB_GATE and my_clkgate in the resulting netlist.

This is the solution. However, you have to set the blackbox attribute on the module like so:

(* blackbox *)
module LIB_GATE (
  input CK,
  input E,
  output ECK);
endmodule

Btw: If you read a .v file with read_verilog -lib then the contents of all modules will be ignored and the blackbox attribute will be set automatically.

You can also read a liberty cell library with read_liberty -lib to get instantiable blackbox cells for everything in your cell library.

Thanks so much for your response. I ended up using the solution involving `read_liberty -lib` as it doesn't require me having to re-define the `LIB_GATE` module. The solution using `(* blackbox *)` also appeared to do the right thing, but I haven't tested `read_verilog`. — FriendFX, Jan 25 '17 at 03:03

How to map clock gate to tech library cell

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