Yosys gives syntax error on 2d interface

Question

I get "syntax error" on 2D interface declaration in Yosys, even with the "-sv" flag.

Is there a way to make Yosys accept the next syntax?

module somename #(
     parameter WDT = 3,
     parameter CNT = 2
) (
     input [WDT-1:0] in_a [CNT-1:0],
     output [WDT-1:0] out_b [CNT-1:0]
);

Thanks!

score 2 · Accepted Answer · answered Jun 30 '17 at 20:15

2

Yosys's read_verilog -sv only supports a tiny subset of SystemVerilog. Array ports are not supported.

If you have access to the Verific library then you can build Yosys with Verific support and use that to read SystemVerilog sources:

verific -sv test.sv
verific -import somename

answered Jun 30 '17 at 20:15

CliffordVienna

Thanks for the response! Just to make sure - I need to buy Verific tool and license before I can actually use it with Yosys, right? There isn't any free package or such of Verific that I am missing? – EEliaz Jul 12 '17 at 19:29
@EEliaz Unfortunately yes. Verific is usually very generous when it comes to eval licences for academia. Not sure if that helps you.. – CliffordVienna Jul 13 '17 at 06:24
Figured that would be the case :) One last question - I guess that in the regular verilog frontend you do some special parsing to support formal verification. Is the Verific command is expected to work well for formal verification use case? – EEliaz Jul 13 '17 at 20:23
Yes. Right now there is only limited support for SVA and PSL via Verific, but we have full support for SVA and PSL on the todo list. I hope to finish that within the next year. – CliffordVienna Jul 14 '17 at 14:44

1 Answers1