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I have a decoder defined in verilog as:

module my_decoder(
    input [3:0] in,
    output reg[19:0] out
    );

    always@(*) begin
        case (in)
            4'd0: out= 20'd114912;
            4'd1: out= 20'd114912;
            4'd2: out= 20'd180324;
            4'd3: out= 20'd409644;
            4'd4: out= 20'd917535;
            4'd5: out= 20'd395532;
            4'd6: out= 20'd137988;
            4'd7: out= 20'd16128;
            4'd8: out= 20'd16128;
            4'd9: out= 20'd16128;
            4'd10: out= 20'd137988;
            4'd11: out= 20'd395532;
            4'd12: out= 20'd917535;
            4'd13: out= 20'd409644;
            4'd14: out= 20'd180324;
            4'd15: out= 20'd114912;
        endcase
    end

endmodule

Now, I want this to be implemented using only logical, standard cells (namely AND, OR, NAND, XOR and NOT). So far I have tried three unsuccessful approaches:

  1. POS/SOP form functions from sympy module (unsuccessful because only AND, OR and NOT is used)

  2. Vivado synthesis (unsuccessful because the design is synthesized using only look up tables).

  3. yosys open source synthesizer (unsuccessful because, apparently, I should write a "toy" .lib file with the physical descriptions of the cells I want to use, which I find to be too much work for what I want to achieve).

Is there a better approach to this problem (or some hack on one of the previous)?

Edit to clarify things, as @Fra93 comment suggests that I have not explain myself well. Some of the results from sympy's SOP are these:

out[0] = in[2] AND (NOT in[3])

out[1] = (in[1] OR in[2]) AND (in[2] OR in[3]) AND (NOT in[1] OR NOT in[2] OR NOT in[3])

... and this just gets more and more complicated. What I want is to tell the tool (or find a tool I can tell it to) to also use NAND and XOR gates, as this will probably simplify the expressions.

gudise
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  • Synopsis synthesis can do it: https://s2.smu.edu/~manikas/CAD_Tools/SDC/lab2/lab2_synopsys_dc.pdf – Mikef Jul 11 '22 at 15:52
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    yosys on [EDAplayground](https://www.edaplayground.com/home) has an "use ABC with cell library" which is a collection of NAND,NOR,NOT,etc. Based on the log the library comes from the example within yosys `/yosys-yosys-0.9/examples/cmos/cmos_cells.lib` – Greg Jul 11 '22 at 17:16
  • I tried implementing it in Vivado and it produces a ROM. Do you expect the synthetizer tool to infer a pattern with your seemingly random outputs? – Fra93 Jul 11 '22 at 20:48
  • @Fra93, it is not exactly a "pattern", but a Boolean function implemented with the minimum number of AND, NAND, OR, XOR and NOT gates. For example, you can make the Boolean function as a minimal set of AND, OR and NOT gates (decomposing each "out" element as the sum of products), but the expressions are too complicated. I suppose that by also using NAND and XOR, the expressions will be more manageable. – gudise Jul 12 '22 at 09:02
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    @gudise I believe the synthetizer would work with wathever equations work best for the FPGA LUTs, that's because its work is to do so, not to simplify things for us humans. Did you check instead this website that calculates the Karnaugh map and a simplification of your boolean input function? http://tma.main.jp/logic/logic.php?lang=en&type=eq&eq=%28A%2B%7EB%29%28A%7EC%2B%7ED%29%2B%7EABCD – Fra93 Jul 12 '22 at 13:54

0 Answers0