3

My current iCE40 FPGA project includes an 8-bit (soft IP) microprocessor connected to a 4Kx8 RAM which is composed from 8 2Kx2 block RAMs. It would be useful to be able to load new programs (for the 8-bit micro) into the 4kx8 RAM without requiring an FPGA recompile or reroute. The proposed flow would need to a) analyze the FPGA netlist to figure out how the 8 2Kx2 block RAMs (that compose the 4Kx8 RAM) are arranged and named. b) split the Intel hex file that contains the new program (for the 8-bit-micro) into 8 sections. c) find each of the 8 block RAM data sections in the bitstream and replace the current content of each section with the new program content. Can anyone from the icestorm or yosys projects please comment if this proposed flow is possible (or if a solution already exists).

CliffordVienna
  • 7,995
  • 1
  • 37
  • 57
scd
  • 51
  • 5

1 Answers1

5

Edit: There is now a tool in IceStorm to do this: icebram

Example usage:

  1. Generate a random hex file for synthesis. Say we have a memory that is 8 bits wide x 512 words deep: icebram -g 8 512 > datafile_syn.hex

  2. Run synthesis (Yosys) and place&route (arachne-pnr). Use $readmemh("datafile_syn.hex", memory); in your Verilog code to initialize the memory.

  3. Replace memory content in the generated IceStorm .asc file: icebram datafile_syn.hex datafile.hex < synout.asc > final.asc

  4. Pack final IceStorm .asc file into binary bit-stream with icepack.

Simply repeat steps 3. and 4. whenever you got a new datafile.hex.

Theoretically this is possible of course, but it's not implemented yet. Afaics the following changes would be required:

1) Yosys' memory_bram pass would need to somehow store the information how a memory in the original design is broken up into individual SB_RAM40_4K cells, preferably by storing this information in attributes on the cells.

2) Arachne-pnr already can create a placelist. This should be extended to also write a file that contains the information from the attributes in 1) plus the relevant placement information.

3) A tool must be written that is using this information to patch the memory content of IceStorm .asc files.

I can do 1) but it would be nice if somebody else would do 2) and 3).

CliffordVienna
  • 7,995
  • 1
  • 37
  • 57
  • 1
    Hi Clifford, Thanks for the reply. For my purposes, I think another solution would work. I think it may be possible to find a solution using only a tool that analyses/modifies the bitstream (with some human intervention). – scd Apr 30 '16 at 15:53
  • 1
    Since we know the initial contents of the RAM of the original bitstream, it should be possible to determine how the block RAMs are arranged (with some human intervention) And once we know how the block RAMs are arranged, we can split the new desired RAM contents and re-write the bitstream contents accordingly. I think I could probably write a tool flow to do what I want based on the bitstream analysis tools that you have already written, but I might need a few hints and some guidance. – scd Apr 30 '16 at 16:06
  • @scd contact me per email at clifford@clifford.at or cliffordvienna@gmail.com and we can discuss how I can support you. – CliffordVienna Apr 30 '16 at 16:09