Generate TIE cells with Yosys?

Question

I am using Yosys to synthesise my RTL design which includes a couple of literal constants, such as tied output ports as in the following code:

module my_module (
    input a,
    input b,
    output c,
    output d);

    assign c = a & b;
    assign d = 1'b1;
endmodule

In this case, output d will obviously always be a logical one. The flow I am using includes the abc -liberty my_stdcells.lib call to map the combinatorial logic to the standard cells provided by the library, followed by the clean and write_verilog calls.

The cell library I am using also provides TIELO and TIEHI cells, but the synthesised Verilog netlist doesn't include any instances of those cells but instead still shows literal constants like in the example above.

I could probably write a script to post-process the synthesised netlist to replace these literals with TIE* cell instances from the library, but I am wondering if I could get Yosys to do that for me somehow, resulting in something like

TIEHI tiehi_d_inst(.Y(d));

for the assign d = 1'b1 line in the code above.

score 2 · Accepted Answer · answered Oct 26 '15 at 13:08

The command you are looking for is hilomap. For example, to map to TIEHI and TIELO cells with Y outputs use something like:

hilomap -hicell TIEHI Y -locell TIELO Y

This will create an individual TIEHI/TIELO cell for each constant bit in the design. Use the option -singleton to only create single TIEHI/TIELO cells with a higher fan-out.

Generate TIE cells with Yosys?

1 Answers1