I'm currently compiling a bitstream for my project in a Makefile.
For the non-debug version of the build I use the following command:
yosys -p "synth_ice40 -blif $@ -top system" $^
And for the debug version I use:
yosys -p "verilog_defaults -add -DDEBUG; synth_ice40 -blif $@ -top system" $^
In the case of the debug build, the command completes, but `DEBUG is not defined when the verilog is read/parsed.
Does verilog_defaults apply to ice40_synth? And if not, is there a way to achieve this without replicating ice40_synth in a script?