How to put a list of cells into a submodule in yosys

Question

I am trying to write a procedure to put each Strongly Connected Component of the given circuit into a distinct sub-module.

So, I tried to add a function to SCC pass in Yosys to add each SCC into a submod. The function is:

  void putSelectionIntoParition (RTLIL::Design *design, 
                 std::vector<pair<std::string,RTLIL::Selection>>& SelectionVector)
  {
    int p_count = 0;
    for (std::vector<pair<std::string,RTLIL::Selection>>::iterator it = SelectionVector.begin();
     it != SelectionVector.end(); ++it) 
      {
    design->selection_stack[0] = it->second;
    design->selection_stack[0].optimize(design);
    std::string command = "submod -name ";
    command.append(it->first);
    Pass::call_on_selection(design, it->second, command); 
    ++p_count;
    } 
  }

However, my code does not work properly. I guess the problem is with "selection" process that I use. I was wondering if there is any utility/API inside the yosys source that accept vector of cells (as well and a name submodule) and put them into a sub-module.

Answer 1

The following should work just fine:

void putSelectionIntoParition(RTLIL::Design *design,
    std::vector<pair<std::string, RTLIL::Selection>> &SelectionVector)
{
    for (auto it : SelectionVector) {
        std::string command = "submod -name " + it.first;
        Pass::call_on_selection(design, it.second, command);
    }
}

You definitely don't need (nor should) modify selection_stack.

I was wondering if there is any utility/API inside the yosys source that accept vector of cells (as well and a name submodule) and put them into a sub-module.

You would do this by setting the submod="<name>" attribute on the cells. Then simply run the submod command.

You might have seen that the scc documentation mentions a -set_attr option that is yet unimplemented. I have now implemented this option in commit ef603c6 (commit 914aa8a contains a bugfix for scc).

With this feature you can now accomplished what you have described using something like the following yosys script.

read_verilog test.v
prep
scc -set_attr submod scc{}
submod
show test

I have tested this with the folling test.v file:

module test(input A, B, output X, Y);
assign X = (A & B) ^ X, Y = A | (B ^ Y);
endmodule

3. Executing SCC pass (detecting logic loops).
Found an SCC: $xor$test.v:2$2
Found an SCC: $or$test.v:2$4 $xor$test.v:2$3
Found 2 SCCs in module test.
Found 2 SCCs.