0

I'm trying to make sense of what yosys is doing to my verilog source, so I have inserted a number of dump processes into my script. I assume that these are in what the manual describes as ILANG? Looking through the dump immediately after reading in the verilog, it seems to me that important things have been lost. For example, I have a set of parameter definitions that map the ascii letter codes. These are listed in the ILANG but with no value.

Is there are documentation that describes the format and interpretation of this output? Yosys seems to discard large parts of my code, and I have so far been unable to determine just how the things it discards relate back to my source code.

Bill Purvis
  • 1
  • 2

2 Answers2

1

Parameters are substituted by the HDL front-end. Inside ILANG we only remember the existence of a parameter, not its value.

Yosys seems to discard large parts of my code

I doubt that. Unless you mean it discards it after it has dealt with the part and its not needed anymore for the further steps. In this case you are of course correct, but I don't see any problem with this behavior. For example, a C compiler also forgets many details about your original C code once it is in a code generation step.

Unfortunately you do not provide an example that demonstrates your point. Please see question 1 in the Yosys F.A.Q. and the mcve howto for how to write an good question.

Community
  • 1
  • 1
CliffordVienna
  • 7,995
  • 1
  • 37
  • 57
  • My code is pretty substantial and probably contains an error which is causing a large portion of the code to be discarded, but as I don't know where the error is, and have so far been unable to correlate the discarded bits with my source I can't make any progress using Yosys. I did send a copy of my source code to you be email, but as you are clearly a busy man I guess it got skipped over as junk mail. I am falling back on using the Quartus development software with an Altera board. Slower than Yosys but messages are more helpful. – Bill Purvis Feb 18 '17 at 11:01
  • I'm looking at your project now. (Sorry for not replying to your email.) Where is your test bench? – CliffordVienna Feb 18 '17 at 11:21
  • I've now got it running on an Altera board, Using Quartus development software. Fixed the bugs, and transferred the verilog back to the Icestick version, slight changes to the top level stuff. Again it simply hangs after moving to the S_CLEAR_1 state. I have no experience with Verilog simulators, but would be happy to learn if you can recommend one. – Bill Purvis Feb 18 '17 at 18:30
0

I have resolved my problem. I don't understand why, but it seems that when the chip is initialised, either by powering up, or by re-programming, the first character, possibly the first two on occasions, is corrupt. I have managed to code up extra states within the code to handle this, so it's not really an answer, but a work-around. I would like to know if the reset signal on the IceStick board is raised to initialise things properly? If not, then that could be the cause of corruption. Once the garbage characters have gone, it all seems to work OK.

Bill Purvis
  • 1
  • 2