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I have problems with programming Xilinx 3an1400 FPGA over JTAG interface.

My custom PCB consists of CPU and FPGA connected in the JTAG chain with CPU on 1-st position and FPGA on second. I can access and program the CPU over JTAG without any problem. When FPGA is alone in the JTAG chain its programming is also successful.

The problems exist only when the FPGA and the CPU are in one chain. Identification the number of the devices in the chain looks OK. Two devices are recognized by the Xilinx Impact tool, but I get the error when trying to perform the read ID command on the FPGA.

I have tried to lower the JTAG frequency to 750Khz with no success. I Got the message :

INFO:iMPACT:583 - '2': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '2':  Device IDCODE :        00001111111111111111111111111110
INFO:iMPACT:1579 - '2': Expected IDCODE:    00000010011000110000000010010011

I connect the logic analyzes and get the signal dump. When FPGA only is connected and everything works as expected I get the next picture from read ID command: Logic analyzer picture dump FPGA only in the chain

When I have TI AM5726 CPU and FPGA in one chain I see the next picture by logging the read ID command: Picture of the JTAG dump with CPU and FPGA connected in the chain

CPU should be bypassed, as 6 ones (length of CPU IR register) has been send, and read ID command looks the same as for the previous example (001001), but response for this command is not as expected.

Probably CPU is not in the bypass and somehow break the TDO signal, but from the sending pattern, it should be. I have also checked the form of the signal with the oscilloscope and it looks OK.

What can be the potential reason of the problem ?

When I run the "Initialize chain" command on the start of the Impact tool, it detects that second device is Spartan 3AN1400, so I suppose that it must somehow performs read id operation during initialization.

rhr
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    Are you sure of your schematic ? Could you add it to the question ? – Nipo Jul 23 '17 at 12:20
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    Can't add it as it is spitted on several pages. What I have also discovered that when i press identify chain button in the Impact both FPGA and CPU are correctly detected and ID can be read. So i suppose that schematic it's OK. I have add the logic analyzer dump for that case. [link](https://image.ibb.co/eN3T2F/initialize_chain.png). But in that case another command are used, just shifting out ID by reading data register. I suppose problem can be that CPU doesn't go into bypass and somehow affects the TDI for FPGA during FPGA read ID command – rhr Aug 09 '17 at 08:09

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