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I am new to VHDL. I was trying to write code for adder subtractor. One of my input bus for the circuity is connected to ground after synthesis. I am using Xilinx ISE 14.2 in Ubuntu 14.04 LTS 64 bit.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity examples is
    Generic(n: Natural :=8);
    port (
          A : in std_logic_vector(n-1 downto 0);
          B : in std_logic_vector(n-1 downto 0);
         subtract : in std_logic;
         sum: out std_logic_vector(n-1 downto 0);
         carry : out std_logic
    );
   end examples;

   architecture Behavioral of examples is
       Signal result: std_logic_vector(n downto 0);
   begin

       my_adder_subtractor : process(A,B,subtract)
           begin
           if(subtract = '0') Then
               result <= std_logic_vector(('0' & unsigned(A))+('0' & unsigned(B)));

           else
               result <= std_logic_vector(('0' & unsigned(A))-('0' & unsigned(B)));
           end if;
           sum <= result(n-1 downto 0);
           carry <= result(n);
       end process my_adder_subtractor;

   end Behavioral;

RTL schematic:

RTL schematic

Paebbels
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Rezwan Khan
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2 Answers2

1

How about this. Let me know if that works. My VHDL goes way back.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity examples is
Generic(n: Natural :=8);
port (
     A : in std_logic_vector(n-1 downto 0);
     B : in std_logic_vector(n-1 downto 0);
     subtract, clk : in std_logic;
     sum: out std_logic_vector(n-1 downto 0);
     carry : out std_logic_vector(0 downto 0)
);
end examples;

   architecture Behavioral of examples is
   begin
      process(clk)
           begin
           if(subtract = '0') then
               (carry, sum) <= ('0' & A)+('0' & B);
           else
               (carry, sum) <= ('0' & A)-('0' & B);
           end if;
      end process;
   end Behavioral;
h3X3n
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  • My question is why port A is connected to ground? Also tried to add 2 signals..same result. May be I am missing something. What should be the data types of the signal? I tried with std logic vector – Rezwan Khan Jul 22 '16 at 22:09
  • Well, multiple thing seem a bit off with your implementation. There should not be a process on (A, B, substract) because a process infers a memory element (D-Latch). It seems wierd to me that it would change state on a trigger of 3 different inputs on which you also make operations. Also I do not understand why you define your inputs as std_logic_vectors when you cast them to unsigned and then to std_logic vector right after. Just define them as unsigned right in the beginning. Unisgned is synthetisable, no need to cast it. – h3X3n Jul 25 '16 at 13:10
  • By the way you do not really need to make a process on the clock signal. I just put it there because you seemed to want a memory element, but I had trouble with it switching states on A, B and substract (making the memory element virtually useless [you could remove the process without changing anything from your behavior]). – h3X3n Jul 25 '16 at 13:37
  • Tried your code. Getting following error ERROR:HDLParsers:3285 - "/home/rezwan/xilinx_projects/free_range_vhdl/examples.vhd" Line 21. No array or record type can be found that has elements of types matching the aggregate. ERROR:HDLParsers:3285 - "/home/rezwan/xilinx_projects/free_range_vhdl/examples.vhd" Line 23. No array or record type can be found that has elements of types matching the aggregate. – Rezwan Khan Jul 25 '16 at 16:37
-1

No A is not connected to ground. The RTL schematic drawings in Xilinx ISE are not good ...

One of the input bits of yours adder's inputs is zero. So A is concatenated with one ground bit. Please open the RTL technology schematic to see the "real" circuit.

Paebbels
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