How do I initiate a Xilinx ISE Block Memory from a raw memory dump?

Question

I dumped the RAM from a working device that I want to partially emulate on an FPGA. In Xilinx ISE I used the Core Generator to generate a RAM module.

Now there is an option to initialise the RAM with a COE file. Unfortunately I can't find any tool that can convert a raw memory dump to a COE file. Or anything to COE for that matter.

What is the best way to do this?

[COE File Syntax](http://www.xilinx.com/itp/xilinx10/isehelp/cgn_r_coe_file_syntax.htm) and [AR# 11744 CORE Generator - Hints for creating COE files for memory cores (Block Memory, Dist Memory, ROM, RAM, etc.)](http://www.xilinx.com/support/answers/11744.html). Also see [How to Initialize BRAM with COE file for Xilinx FPGA](http://tipsarea.com/2014/05/21/how-to-initialize-bram-with-coe-file-for-xilinx-fpga/) if your version of ISE blocks the Memory editor access from the GUI. Found googling *COE Xilinx ISE*. — , Oct 03 '16 at 20:02
[COEGen v0.01 – Generate .coe files from binary files for Xilinx FPGA block RAM](https://wornwinter.wordpress.com/2015/02/07/coegen-v0-01-generate-coe-files-from-binary-files-for-xilinx-fpga-block-ram/). This googling with search terms *binary to COE format Xilinx*. — , Oct 04 '16 at 07:25
[SRecord 1.64](http://srecord.sourceforge.net/download.html) requires libboost (so does COEGen), same googling search term. — , Oct 04 '16 at 07:39
SRecord seems to be just the thing I need. I tried several variations of your search terms... turns out *sometimes* the second page contains something useful. (at least in my filter bubble) — Pepijn, Oct 08 '16 at 09:26

score 1 · Answer 1 · answered Oct 04 '16 at 22:55

Initializing BRAM in a FPGA can be done using CORE generator, but I prefer to write VHDL so that the synthesis tool infers a BRAM or lookup table (LUT). Note, I never use Core Gen for creating/initializing RAM.

I'm not sure how the data is formatted, but here's a VHDL code snippet on how to read a text file where each line contains a binary string and creates a signal with the file contents. You'll have to know the format of the file beforehand and the length of it.

-- define a type for the lookup table (LUT)
type lut_type is array(0 to 2**12-1) of std_logic_vector(15 downto 0);

impure function init_lut_from_file(lut_file_name : in string)
    return lut_type is
    FILE lut_file       : TEXT open READ_MODE is lut_file_name;
    variable lut_line   : line;
    variable bv_temp    : bit_vector(15 downto 0);
    variable lut        : lut_type;
begin
    for i in lut_type'range loop
        readline(lut_file, lut_line);
        read(lut_line, bv_temp);
        lut(i) := to_stdlogicvector(bv_temp);
    end loop;
    return lut;
end function;

signal lut         : lut_type := init_lut_from_file("c:\data.txt");

The above impure function will read c:\data.txt containing 16-bit binary strings on each line of the file into a LUT with 2^12 = 4096 entries.

You can then write additional code to read & write to lut as usual.

Is that synthesizeable? It'd work great for ROM and read-only simulation at least, and in the super super final design RAM won't need to be initialised. — Pepijn, Oct 08 '16 at 09:19
Yes, I've used this code to implement a lookup table in Xilinx FPGAs using the ISE design suite and tested in a Virtex6 FPGA. — David K, Oct 10 '16 at 03:59

How do I initiate a Xilinx ISE Block Memory from a raw memory dump?

1 Answers1