Coding error for vivado project

Question

I wanted to synthesis this coding, but it keep telling me that there is error at "reg button_old, button_raise;". Is there anyone who knows what mistakes I have in the coding? Thank you very much for your help. We are doing project using nexys 4, we are able to simulate the coding, but are unable to synthesis it so we are not able to proceed to the next steps. Hope someone can help us.

`timescale 1ns / 1ps

module Player (input clk, input rst,input button, input [29:0] set, input button_p1, input button_p2, output [3:0]oscore1, output [3:0]oscore2, output LED_ON, output answer, output [3:0]seg1, output [3:0]seg2)
    reg button_old, button_raise;
    reg number;
    reg [3:0] Score_P1, Score_P2;
    wire [3:0] Score_P1, Score_P2;
    reg [6:0] sevseg;
    wire answer;
    reg Clk_10000;
    reg [31:0] count;
    reg [3:0] digit;
    output [3:0] digit;

    always @(posedge clk or posedge rst) begin
        // detect rising edge
        button_old = 0;
        button = 0;
        button_raise =1'b0;
        if (button_old != button && button == 1'b1)
            button_raise <= 1'b1
        button_old <= button;
        // increment number
        if(button_raise == 1b'1)
        begin
          Score_P1 = 4'b0000;
          Score_P2 =4'b0000;
            if(~rst) number <= 0;
            else if(button_p1 && !button_p2 && answer==1'b1)
                         Score_P1 <= (Score_P1 + 1);
            else if(button_p2 && !button_p1 && answer==1'b1)
                         Score_P2 <= (Score_P2 + 1);
            else if(button_p1 && button_p2 && answer==1'b1 || answer==1'b0)
                        LED_ON [0];
            else LED_ON [7];
        end
        end
        end else
        button <=0;
        button_old <=0;
        button_raise <=0;

    end

    assign oscore1= Score_P1;
    assign oscore2= Score_P2;

    always @ (rd_ptr) begin
    set = setlist[rd_ptr];
    assign answer = set [totlen-1];
    case (digit)
    4'b1000: sevseg = set [27:21];
    4'b0100: sevseg = set [20:14];
    4'b0010: sevseg = set [13:7];
    4'b0001: sevseg = set [6:0];
    default: sevseg= 7'b0000000;
    endcase

    assign setlist[0] <= 29'b01111110100110011111101001111;
    assign setlist[1] <= 29'b11111110100111111111101001111;
    assign setlist[2] <= 29'b01111110000000111111100000000;
    assign setlist[3] <= 29'b01111110100111111111100100000;
    end

    always@(digit or seg1 or seg2) begin
    case(digit)
    4'b1110: sevseg = seg1[41:35];
    4'b1101: sevseg = seg1[34:28];
    4'b1011: sevseg = seg2[27:21];
    4'b0111: sevseg = seg2[20:14];
    endcase
    end

    always @ (posedge Clk or negedge rst) begin
    if (!rst) begin
    count <= 32'd0;
    Clk_10000<=0;
    end else begin
    if (count == 'd10000) begin
    count <= 32d'0;
    Clk_10000 <= ~Clk_10000;
    end else begin
    count <= count +1;
    end
    end
    end

    always @ (posedge Clk_10000 or negedge rst) begin
    if (!rst) begin
    digit <= 4'b1110;
    end else if (Clk_10000) begin
    digit <= {digit [2:0], digit [3]};
    end
    end

    always @ (Score_P1)
    begin
    case (Score_P1)
     4'b0000: seg1 <= 14'b0000001_0000001;
     4'b0001: seg1 <= 14'b0000001_1001111;
     4'b0010: seg1 <= 14'b0000001_0010010;
     4'b0011: seg1 <= 14'b0000001_0000110;
     4'b0100: seg1 <= 14'b0000001_1001100;
     4'b0101: seg1 <= 14'b0000001_0100100;
     4'b0110: seg1 <= 14'b0000001_0100000;
     4'b0111: seg1 <= 14'b0000001_0001111;
     4'b1000: seg1 <= 14'b0000001_0000000;
     4'b1001: seg1 <= 14'b0000001_0001100;
     4'b1010: seg1 <= 14'b1001111_0000001;
     4'b1011: seg1 <= 14'b1001111_1001111;
     4'b1100: seg1 <= 14'b1001111_0010010;
     4'b1101: seg1 <= 14'b1001111_0000110;
     4'b1110: seg1 <= 14'b1001111_0100100;
     4'b1111: seg1 <= 14'b1001111_0100000;
    endcase
    end

    always @ (Score_P2)
    begin
    case (Score_P2)
    4'b0000: seg2 <= 14'b0000001_0000001;
     4'b0001: seg1 <= 14'b0000001_1001111;
     4'b0010: seg2 <= 14'b0000001_0010010;
     4'b0011: seg2 <= 14'b0000001_0000110;
     4'b0100: seg2 <= 14'b0000001_1001100;
     4'b0101: seg2 <= 14'b0000001_0100100;
     4'b0110: seg2 <= 14'b0000001_0100000;
     4'b0111: seg2 <= 14'b0000001_0001111;
     4'b1000: seg2 <= 14'b0000001_0000000;
     4'b1001: seg2 <= 14'b0000001_0001100;
     4'b1010: seg2 <= 14'b1001111_0000001;
     4'b1011: seg2 <= 14'b1001111_1001111;
     4'b1100: seg2 <= 14'b1001111_0010010;
     4'b1101: seg2 <= 14'b1001111_0000110;           
     4'b1110: seg2 <= 14'b1001111_0100100;
     4'b1111: seg2 <= 14'b1001111_0100000;
    endcase
    end
    endmodule

Your code has a tremendous number of syntax errors including missing `;`, duplicate declarations, poorly formed numeric literals. I doubt you simulated this. — dave_59, Dec 04 '17 at 08:21
From eyeballing it, there are around 20 some errors, at least 7 unique error types. Errors include missing `;`, malformed statements, inferred latches, procedural continuous statements, asynchronously using a clock signal, multi declaration, incorrect usage of blocking/non-blocking assignments, etc. If you are on fpga, does your board supposed flops with asynchronous reset? Always simulate before you synthesis. — Greg, Dec 04 '17 at 16:00

score 1 · Answer 1 · answered Dec 04 '17 at 23:34

Okay, let's do this:

1. You're missing a semicolon after your module ports description.

module Player (
    input clk,
    input rst,
    input button,
    input [29:0] set,
    input button_p1,
    input button_p2,
    output [3:0]oscore1,
    output [3:0]oscore2,
    output LED_ON,
    output answer,
    output [3:0]seg1,
    output [3:0]seg2);

2. You also can't declare all your inputs/outputs at the top in the module definition, and declare this output lower down:

output [3:0] digit;

So move that up with the other outputs.

3. You're missing a semicolon here:

button_raise <= 1'b1

4. This is a typo, it needs to be 1'b1:

if(button_raise == 1b'1)

Same with this:

count <= 32d'0;

5. This doesn't do anything:

LED_ON [0];
else LED_ON [7];

I think you mean to assign LED_ON[0] <= 1'b1 and LED_ON[7] <= 1'b1.

However, you've also defined LED_ON as only 1-bit, so I'm assuming you want to define it as:

output reg [7:0] LED_ON,

6. You're also missing an end statement somewhere, probably because you're trying to do if statements for multiple lines that aren't wrapped in a begin and end, like here:

end else
button <=0;
button_old <=0;
button_raise <=0;

7. You're using blocking assignments = in a sequential block which isn't allowed like here:

always @(posedge clk or posedge rst) begin
    // detect rising edge
    button_old = 0;

So make these non-blocking assignments like <=.

8. You're trying to do nonblocking assignments in a combinational block:

always @ (rd_ptr) begin
    //...
    assign setlist[0] <= 29'b01111110100110011111101001111;

So make these blocking assignments like =.v

9. You're trying to do assignments in a combinational block like here:

always @ (rd_ptr) begin
    set = setlist[rd_ptr];
    assign answer = set [totlen-1];

There make the assignments outside of the always block or get rid of the assign altogether.

10. These signals aren't defined anywhere. So the compiler doesn't know what to do with them.

Clk;
rd_ptr;
setlist;
totlen;

11. Score_P1 and Score_P2 have both been defined twice as both a register and a wire.

reg [3:0] Score_P1, Score_P2;
wire [3:0] Score_P1, Score_P2;

Same with the output/wire answer.

12. You're assigning to your input button like it's a register. That doesn't make any sense. You're only ever assigning it as 0 so get rid of the assignments and just let it be an input.

You're also assigning to your input set.

13. You're assigning to setlist in a combination block like it's a reg, but you've defined it as a wire. So define it as a reg.

14. You've also defined setlist as a single bit but you're indexing on it as [0] to [3] so let's define it as 4 bits. You're also assigning each index with with 29 bits. So let's call it a 2d array, even though it's never even read from and this makes no sense.

15. seg1 and seg2 are defined as 4-bits, but you're indexing on them all the way up to [41:35], so let's call them both 42-bits.

And there you have it, with 15+ easy fixes, now your code that makes no sense and probably does nothing still makes no sense and does nothing, but can actually compile. Final result:

`timescale 1ns / 1ps

module Player (
    input wire clk,
    input wire rst,
    input wire button,
    input wire [29:0] set,
    input wire button_p1,
    input wire button_p2,
    output wire [3:0]oscore1,
    output wire [3:0]oscore2,
    output reg [7:0] LED_ON,
    output reg answer,
    output reg [3:0] digit,
    output reg [42:0]seg1,
    output reg [42:0]seg2
);

wire  Clk;
wire  rd_ptr;
reg [28:0] setlist [3:0];
wire  totlen;


reg button_old, button_raise;
reg number;
reg [3:0] Score_P1, Score_P2;
reg [6:0] sevseg;
reg Clk_10000;
reg [31:0] count;

always @(posedge clk or posedge rst) begin
    // detect rising edge
    button_old <= 0;
    button_raise <= 1'b0;
    if (button_old != button && button == 1'b1) begin
        button_raise <= 1'b1;
        button_old <= button;
        // increment number
        if(button_raise == 1'b1) begin
            Score_P1 = 4'b0000;
            Score_P2 =4'b0000;
            if(~rst) begin
                number <= 0;
            end
        end else if(button_p1 && !button_p2 && answer==1'b1) begin
            Score_P1 <= (Score_P1 + 1);
        end else if(button_p2 && !button_p1 && answer==1'b1) begin
            Score_P2 <= (Score_P2 + 1);
        end else if(button_p1 && button_p2 && answer==1'b1 || answer==1'b0) begin
            LED_ON [0] <= 1'b1;
        end else begin
            LED_ON [7] <= 1'b1;
        end
    end else begin
        button_old <=0;
        button_raise <=0;
    end
end

assign oscore1= Score_P1;
assign oscore2= Score_P2;

always @ (rd_ptr) begin
    assign answer = set [totlen-1];
    case (digit)
        4'b1000: sevseg = set [27:21];
        4'b0100: sevseg = set [20:14];
        4'b0010: sevseg = set [13:7];
        4'b0001: sevseg = set [6:0];
        default: sevseg= 7'b0000000;
    endcase

    setlist[0] = 29'b01111110100110011111101001111;
    setlist[1] = 29'b11111110100111111111101001111;
    setlist[2] = 29'b01111110000000111111100000000;
    setlist[3] = 29'b01111110100111111111100100000;
end

always@(digit or seg1 or seg2) begin
    case(digit)
        4'b1110: sevseg = seg1[41:35];
        4'b1101: sevseg = seg1[34:28];
        4'b1011: sevseg = seg2[27:21];
        4'b0111: sevseg = seg2[20:14];
    endcase
end

always @ (posedge Clk or negedge rst) begin
    if (!rst) begin
        count <= 32'd0;
        Clk_10000<=0;
    end else begin
        if (count == 'd10000) begin
            count <= 32'd0;
            Clk_10000 <= ~Clk_10000;
        end else begin
            count <= count +1;
        end
    end
end

always @ (posedge Clk_10000 or negedge rst) begin
    if (!rst) begin
        digit <= 4'b1110;
    end else if (Clk_10000) begin
        digit <= {digit [2:0], digit [3]};
    end
end

always @ (Score_P1)
begin
    case (Score_P1)
        4'b0000: seg1 <= 14'b0000001_0000001;
        4'b0001: seg1 <= 14'b0000001_1001111;
        4'b0010: seg1 <= 14'b0000001_0010010;
        4'b0011: seg1 <= 14'b0000001_0000110;
        4'b0100: seg1 <= 14'b0000001_1001100;
        4'b0101: seg1 <= 14'b0000001_0100100;
        4'b0110: seg1 <= 14'b0000001_0100000;
        4'b0111: seg1 <= 14'b0000001_0001111;
        4'b1000: seg1 <= 14'b0000001_0000000;
        4'b1001: seg1 <= 14'b0000001_0001100;
        4'b1010: seg1 <= 14'b1001111_0000001;
        4'b1011: seg1 <= 14'b1001111_1001111;
        4'b1100: seg1 <= 14'b1001111_0010010;
        4'b1101: seg1 <= 14'b1001111_0000110;
        4'b1110: seg1 <= 14'b1001111_0100100;
        4'b1111: seg1 <= 14'b1001111_0100000;
    endcase
end

always @ (Score_P2)
begin
    case (Score_P2)
        4'b0000: seg2 <= 14'b0000001_0000001;
        4'b0001: seg1 <= 14'b0000001_1001111;
        4'b0010: seg2 <= 14'b0000001_0010010;
        4'b0011: seg2 <= 14'b0000001_0000110;
        4'b0100: seg2 <= 14'b0000001_1001100;
        4'b0101: seg2 <= 14'b0000001_0100100;
        4'b0110: seg2 <= 14'b0000001_0100000;
        4'b0111: seg2 <= 14'b0000001_0001111;
        4'b1000: seg2 <= 14'b0000001_0000000;
        4'b1001: seg2 <= 14'b0000001_0001100;
        4'b1010: seg2 <= 14'b1001111_0000001;
        4'b1011: seg2 <= 14'b1001111_1001111;
        4'b1100: seg2 <= 14'b1001111_0010010;
        4'b1101: seg2 <= 14'b1001111_0000110;
        4'b1110: seg2 <= 14'b1001111_0100100;
        4'b1111: seg2 <= 14'b1001111_0100000;
    endcase
end
endmodule

Coding error for vivado project

1 Answers1