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I have a variable in systemverilog that I am setting from a task and reading from another task. The read and the writes are independent. I want to ensure if both read and write are called at the same timestamp I get the updated value.

I can see that by design, this is going into a race condition where I have no control on what the read value would be. I am aware of non-blocking assignment that would ensure I always get the old value of the variable. Is there something with which I can ensure I get the new value of the variable.

I am using system verilog/UVM.

Any suggestion/pointers is highly appreciated :)

Matthew Taylor
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justrajdeep
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1 Answers1

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Since you say you're using the UVM, I assume this is inside your testbench code. And since you are using a task, you can call uvm_wait_for_nba_region() before reading the variable and you'll get the new value regardless a blocking or non-blocking assignment was made to the variable. uvm_wait_for_nba_region() simply blocks waiting for an event triggering by a non-blocking assignment.

Of course, this also assumes there are no other calls to uvm_wait_for_nba_region() in the thread that writes to the variable. But this is the best answer I can give with the limited information you've provided.

dave_59
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