How to write a Verilog function that determines if all elements in an array are equal?

Question

Let's say I have N registers and I want a function that checks if all register contents are equal. How do I write that without having to spell out every single element?

function equal (input [0:N-1][width-1:0] in);
    equal = (???) ? 1'b1 : 1'b0;
endfunction

Answer 1

A simple for loop is one way:

module tb;

parameter N = 8;
parameter width = 4;

reg [0:N-1][width-1:0] arr;

initial begin
    for (int i=0; i<N; i++) arr[i] = 5;
    $display(equal(arr));
    for (int i=0; i<N; i++) arr[i] = 2*i;
    $display(equal(arr));
end

function equal (input [0:N-1][width-1:0] in);
    for (int i=1; i<N; i++) begin
        if (in[i] !== in[0]) return 0;
    end
    return 1;
endfunction

endmodule

Output:

1
0

Answer 2

module tb;

parameter W = 8;
parameter N= 4;

logic [N-1:0][W-1:0] in0, in1;
logic res;

initial begin
    in0 = {8'd6,8'd6,8'd6,8'd6};
    in1 = {8'd6,8'd6,8'd55,8'd6};

    res = equal(in0);
    $display(res);
    res = equal(in1);
    $display(res);  
end

function logic equal(input logic [N-1:0][W-1:0] in);
    equal = (in === {N{in[0]}}) ? 1 : 0;
endfunction

endmodule

Modelsim results:

# 1
# 0