Convert unsigned int to Time in System-verilog

Question

I have in large part of my System-Verilog code used parameters to define different waiting times such as:

int unsigned    HALF_SPI_CLOCK = ((SYSTEM_CLK_PERIOD/2)*DIVISION_FACTOR); //DEFINES THE TIME

Now since I define a timescale in my files I can directly use these params to introduce waiting cycles:

`timescale 1ns/1ns
initial begin
    #HALF_SPI_CLOCK; 
end

Now I want to have time-specified delays everywhere. Means that the simulation will still respect all the timings even if I change the timescale. I would like to keep the parameters but wherever I have a wait statement, I need to specify the time. Something like

#(HALF_SPI_CLOCK) ns;

But this is not accepted by Modelsim. Is there a way to cast a parameter or an Unsigned int to a variable of type time in System-Verilog? Is there a way to specify the time unit? I have looked around but could not find any workaround. The reason why I want to have control over the time and make it independent from the timescale is because I intend to change thetimescale later to try to make my simulation faster. Other recommendations or thoughts are very welcome*

I would consider using `timeunit 1ns` inside each module, then no need to worry about the last call to `timescale. — Morgan, Jul 21 '14 at 12:31

Victor Lyuboslavsky · Answer 1 · 2014-07-21T13:42:04.407

5

It is possible to pass time as a parameter in SystemVerilog, like:

module my_module #(time MY_TIME = 100ns);

  initial begin
    #MY_TIME;
    $display("[%t] End waiting", $time);
  end

endmodule

Or use multiplication to get the right time units, like:

module my_module2 #(longint MY_TIME = 100);

  initial begin
    # (MY_TIME * 1us);
    $display("[%t] End waiting 2", $time);
  end

endmodule

See runnable example on EDA Playground: http://www.edaplayground.com/x/m2

edited Jul 21 '14 at 13:42

answered Jul 21 '14 at 12:29

Victor Lyuboslavsky

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Yes that is right. However I sometimes I need to derive a waiting time from different parameters I have in my module. The calculation is done on run-time of some important waiting periods and therefore I need to cast - on the fly - to a TIME variable... – Theo Jul 21 '14 at 13:13
1

@MehdiTabs Using multiplication is probably the best solution here. – Victor Lyuboslavsky Jul 21 '14 at 13:43

score 2 · Answer 2 · answered Jul 21 '14 at 12:27

2

This will simulate and do what you want. While not the most elegant, it works.

task wait_ns(int num);
  repeat (num) #1ns;
endtask 

...

wait_ns(HALF_SPI_CLOCK);

This could have a negative impact simulation speed depending on how the timescale, clock events, and the unit of delay relate to each other.

answered Jul 21 '14 at 12:27

dwikle

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Thanks @dwikle Actually the best option I found so far is to multiply by 1ns. I first create `unsigned int waiting_abs` then I calculate it using different timing parameters. I also create `time waiting_ns`. Then it is easy to cast => `waiting_ns = waiting_abs * 1ns;` – Theo Jul 21 '14 at 13:21

Convert unsigned int to Time in System-verilog

2 Answers2