I'm using a library to share data between C++, VHDL, and SystemVerilog. It uses codegenerators to build datastructures that contain the appropriate field. Think of a c type data structure. I want to generate python code that contains the datastructure and read/write functions to set and write the contents of the datastructure from a / to a file.
To do this i am trying to write a program that prints all the variables in the baseclass with updates from the subclass, but without the subclass variables.
The idea being that class A is the actual VHDL/SystemVerilog/C++ record/structure and class B contains logic to do processing and generate the values in class A.
For example:
class A(object):
def __init__(self):
self.asd = "Test string"
self.foo = 123
def write(self):
print self.__dict__
class B(A):
def __init__(self):
A.__init__(self)
self.bar = 456
self.foo += 1
def write(self):
super(B, self).write()
Calling B.write() should yield the following: (Note the incremented value of foo)
"asd: Test String, foo: 124"
but instead it yields
"asd: Test String, bar: 456, foo: 124".
Is there a way to only get the base class variables? I could compare the base dictionary with the subclass dictionary and only print the values that appear in both but this does not feel like a clean way.