Implicit net-type declaration and `default-nettype

Question

I have a question on `default_nettype directive of SystemVerilog.

By default, the following code is ok.

module m1 (
   input  logic i1,
   output logic o1
   );

   logic  l1;
   assign l1 = i1;
   assign o1 = l1;
endmodule

However, when I change the default net type to none:

`default_nettype none

only i1 causes an error:

ERROR: [VRFC 10-1103] net type must be explicitly specified for i1 when default_nettype is none ...

My question is why only input logic i1 causes an error and requires explicit wire, but output logic o1 and logic l1 does not.

Answer 1

Verilog has too many implicit rules to accommodate lazy programmers (i.e. people who were interested in designing hardware, not writing software)

This error is explained in section 23.2.2.3 Rules for determining port kind, data type, and direction

For the first port in an ANSI style port list:

• If the port kind is omitted:
  • For input and inout ports, the port shall default to a net of default net type. The default net type can be changed using the `default_nettype compiler directive

This implicit 'net' port rule is the opposite of what is used when declaring output ports, and all other declarations outside of ports. The reason behind this is that input ports are an overwhelmingly majority of ports used in a module, and keeping ports connections as wires allows for port collapsing, which is more efficient for simulation.

Answer 2

This is the confusing part of SystemVerilog. Your code works on my simulator, that outputs a warning instead of an error.

If you dive enough in help messages you get that the "type" of the identifier (as in net versus var, opposing to "datatype" which is logic or whatever else) is context sensitive, and specifically input ports are by default nets, while output ports are by default variables. This means that with "default_nettype none" all your input ports are effectively not fully described, because the compiler does not know the resolution function for the net (you might want a wand, for example). Your output ports, being variables, need no resolution function and so no error is thrown there.

Since you cannot really connect the same port to more than one signal unless you really try to this seems redundant to me, but it might be needed due to net coercion rules for elaboration if the input net is driven by more than one assign elsewhere in the design.

My understanding is that "default_nettype none" is mostly used to ensure you do not have undeclared identifiers (leading to width mismatch due to single bit inference) and a port is declared, so you might check if your tool has the option of inferring a wire for ports anyway (again, my simulator outputs a warning and does this by default, and the synthesizer does not complain either).

Other than that, the only workaround I see is going for "default_nettype none" first thing after the ANSI port declaration and "default_nettype wire" last thing before endmodule, in every module. We cannot do that, as per 1800-2017 22.8:

The directive `default_nettype controls the net type created for implicit net declarations (see 6.10). It can be used only outside design elements.

The reference for implicit net declaration is section 6.10 in IEEE 1800-2017, although following the mentioned sections from there seems to point to non-ANSI declarations only... you might need a deeper dive to fully understand the matter.