Passing string values to SystemVerilog parameter

Question

I have a problem in passing a string value to a generic parameter in SystemVerilog. The modules are instantiated as shown below. The memory writes some values to FILE_OUT, which is a generic parameter. I need to produce two different files - "file1.txt" and "file2.txt", for different instances of the memory.

Initially I tried to use `define directive:

if(ch_ID==1)
  `define FILE_OUT file1.txt
else
  `define FILE_OUT file2.txt 

But, since `define creates global macros, simulation was always giving the output "file2.txt"

Then I tried passing file name as a parameter

if(ch_ID==1)
  parameter FILE_OUT= "file1.txt"
else
  parameter FILE_OUT= "file2.txt"

memory #(.FILE_OUT (FILE_OUT)) mem

This gives me the error- "FILE_OUT" should be a constant value".

Doesn't SV support string values as parameter? If not, why is it accepting a string value when I use `define ?

Could someone help me in solving this problem?

Answer 1

You did not show enough code to know exactly what the cause of the problem might be. You cannot have statement FILE_OUT = "string"l wihout some other context. What you should do is

module #(int ch_ID) component1(...);

localparam string FILE_OUT = $sformatf("file%0d.txt",ch_ID);

memory #(.FILE_OUT (FILE_OUT)) m1(...);

endmodule

Answer 2

The if condition is inferring a generate block and the parameters are being locally scoped.

if(ch_ID==1)
   parameter FILE_OUT= "file1.txt"; // scope: genblk1.FILE_OUT
else
   parameter FILE_OUT= "file2.txt"; // scope: genblk2.FILE_OUT
// parent scope: genblk1.FILE_OUT and genblk2.FILE_OUT exist, not FILE_OUT

Solution, inline the operation:

parameter FILE_OUT= (ch_ID==1) ? "file1.txt" : "file2.txt";
// FILE_OUT exists in the module's scope with the desired name

Example on edaplayground