SVA:Clock gating during SV assertion

Question

I have an SV assertion which checks the property as below

propert my_property;
@(posedge clk) disable iff(reset) $rose(halt) ##0 ((rx_prio) > (expec_prio)) ##[0:$] $rose(rdy) |-> ##[1:100] (my_prio[rx_prio]==1'b1);
endproperty:my_property

I have the assertion as below:

MY_PROPERTY_CHECK:assert property (my_propert)
else
$error;

Here, the scenario is that, the antecedent is true and the consequent is checked between 1 & 100 clock cycles. After the antecedent, the clock is stopped due to clock gating for some time and then the clock starts ticking again. The signal my_prio[rx_prio] is asserted after the clock gating but again within 100 clock cycles. But I still get the assertion failure.

Not able to figure out the issue of failure. Does the clock gating in between the assertion check has an issue? Or any other reason failure? Thanks.

Greg · Accepted Answer · 2017-12-18T21:40:49.313

There might be many threads starting. Try using local variables with display statements below. See IEEE Std 1800-2012 § 16.10 Local variables

propert my_property;
  static int prop_cnt=0; // shared
  local  int prop_id; // Note: some require the "local", other need it omitted
  @(posedge clk) disable iff(reset) 
    ($rose(halt) ##0 ((rx_prio) > (expec_prio)),
        prop_id=prop_cnt++,
        $display("Spawn prop_id:%0d prop_cnt:%0d @ %0t %m",
                   prop_id,prop_cnt,$time) )
    ##[0:$] ($rose(rdy),
        $display("Trigger prop_id:%0d prop_cnt:%0d @ %0t %m",
                     prop_id,prop_cnt,$time) )
    |-> ##[1:100] (my_prio[rx_prio]==1'b1,
        $display("Pass prop_id:%0d prop_cnt:%0d @ %0t %m",
                     prop_id,prop_cnt,$time) );
endproperty : my_property

If you see Spawn-Spawn-Trigger, or Spawn-Trigger-Trigger, our anything outside of expected (i.e. Spawn-Triger-Pass) then there are unexpected threads.

If this is the case, then look into IEEE Std 1800-2012 § 16.9.8 First_match operation

first_match(
    $rose(halt) ##0 ((rx_prio) > (expec_prio)) ##[0:$] $rose(rdy),
      $display("Spawn-Trigger prop_id:%0d prop_cnt:%0d @ %0t %m",
                   prop_id,prop_cnt,$time)

) |-> // ...

OR § 16.9.10 Sequence contained within another sequence

(
    ( $rose(halt) ##0 ((rx_prio) > (expec_prio)) ) within $rose(rdy)[->1],
      $display("Spawn-Trigger prop_id:%0d prop_cnt:%0d @ %0t %m",
                   prop_id,prop_cnt,$time)
) |-> // ...

You might want to create a sequence for the trigger.

Tried the first_match, as the occurrence of `rdy` was many before occurrence of the consequent. And this works. Thanks. — Suhas, Mar 05 '14 at 05:29

score 0 · Answer 2 · answered Mar 04 '14 at 11:16

0

As I don't know your setup, I could assume that you are maybe triggering on a clock further up the hierarchy that is not being gated, but you debug waves in the exact hierarchy where the clock is being gated.

If you are writing your assertions for an RTL block that cannot be retrofitted with assertions (it's VHDL/Verilog or you are not allowed to touch the file), use bind to instantiate your assertions inside that block: http://www.asic-world.com/systemverilog/assertions22.html

answered Mar 04 '14 at 11:16

Tudor Timi

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I have single clock at which the assertion is triggered and don't have any clock further up the hierarchy. And only this clock is gated. – Suhas Mar 04 '14 at 12:08
From the waves, I see that the assertion is triggered before gating (antecedent is satisfied) and the assertion failure is seen after the gating(consequent fails). – Suhas Mar 04 '14 at 12:28
1

Just a shot in the dark, but if you spawn of a thread that prints something at every posedge of clk, do you see that executing during gating? Something like "always @(posedge clk) $display("time = %t", $time);" – Tudor Timi Mar 04 '14 at 14:18

SVA:Clock gating during SV assertion

2 Answers2