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I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks correct in terms of functionality. However, the following module uses a large amount of logic elements. It uses 24 logic elements and I'm not sure why since it should be using 8 + a couple of combinational gates for the case block.

I suspect the adder but I'm not 100% sure. If my suspicion is correct however, is it possible to use multipliers as a simple adder?

module alu #(parameter N = 8)
(
    output logic [N-1:0] alu_res,
    input [N-1:0] a,
    input [N-1:0] b,
    input [1:0] op,
    input clk
);       

wire [7:0] dataa, datab;
wire [15:0] result;

// instantiate embedded 8-bit signed multiplier
mult mult8bit (.*);

// assign multiplier operands
assign dataa = a;
assign datab = b;

always_comb
    unique case (op)
        // LW
        2'b00:  alu_res = 8'b0;
        // ADD
        2'b01:  alu_res = a + b;
        // MUL
        2'b10:  alu_res = result[2*N-2:N-1]; // a is a fraction
        // MOV
        2'b11:  alu_res = a;
    endcase

endmodule
Greg
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geft
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    This might get a better answer over at [Electronics SE](http://electronics.stackexchange.com/). – Polynomial Mar 10 '14 at 15:19
  • Thanks. I've always used stackoverflow. Didn't know others exist. – geft Mar 10 '14 at 15:36
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    `unique` for synthesis means `parallel_case` and `full_case`. Try it with `priority` (only `full_case`) instead. Also try it without a keyword in front of the case statement. – Greg Mar 10 '14 at 15:40
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    @geft There are loads of them! Maths, English Language, Security, Cycling, Philosophy, Physics, Computer Science, Unix & Linux, Superuser, ServerFault, Gaming, User Experience, DB Admin, Parenting, Cooking, Android, Christianity, LaTeX, Game Development, Home Improvement... the list goes on! Take a look at the very bottom of the page for a shortlist :) – Polynomial Mar 10 '14 at 15:41
  • @Polynomial I guess I've never noticed them. I got here through googling. :) – geft Mar 10 '14 at 18:32
  • @geft Took me a long time to realise there were others (excluding SF / SU) too. Once I did... the smaller ones are awesome! :D – Polynomial Mar 10 '14 at 19:20

1 Answers1

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Your case statement will generate a 4 input mux with op as the select which uses a minimum of 2 logic cells. However since your assigning an 8-bit variable in the case block you will require 2 logic elements for each bit of the output. Therefore total logic elements is 8*2 for the large mux and 8 for the adder giving you 24 as the total.

I'm doing this project too so I won't give too much away about how to optimise this. However what I will tell you is that both the mux's and the adder can be implemented using multipliers, 8 at most. With that said I don't think this architecture is optimal for a multiplier implementation.

Lewis R
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