Highest Voted 'rocket-chip' Questions

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TIMESCALEMOD verilator error when attempting to add a new black box in chisel

I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator. My changes pass chipyard's scala compilation phase in which the chisel hardware specification is compiled into verilog.…

asked Jul 28 '22 at 03:17

benjaminou4412

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How to assign data to a register in chisel?

I initialized two registers in my accelerator like val one = RegInit(0.U(5.W)) val two = RegInit(0.U(5.W)) If I have loaded a data to my rs1(R-type instruction) in my C test code, I wanted to assign this value to my self-defined register 'one'. I…

riscv chisel rocket-chip

asked May 23 '22 at 10:43

Lei Niu

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Timescale missing on the module as other modules have it Verilator error

I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the basic GCD code. I then replaced the GCD with an accelerator which has it's own Config, Parameters…

scala chisel rocket-chip verilator

asked Mar 19 '22 at 01:18

CV_Ruddha

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Why would FifoFixer's `stall` signal go high forever?

I'm attempting to do these rather large DMA transfers over the frontbus to memory. The frontbus is ready and no other clients are contending for the front bus at the moment this occurs. My AXI client connected in its 15th 2kB transfer is unable to…

chisel rocket-chip

asked Mar 15 '22 at 21:57

metzkorn

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Adding an MMIO peripheral to Rocket-chip as a submodule

I followed the MMIO Peripherals page from the Chipyard documentation to learn about adding modules to rocket-chip within Chipyard framework - and all that seems to have worked pretty well. I summed up my experiences and tried to write it in a slower…

riscv chisel rocket-chip

asked Feb 23 '22 at 13:15

apaj

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What are these `a.bits.user.amba_prot` signals and why are they only uninitialized conditionally in my HarnessBinder?

Context: I began using Chipyard about a month back to facilitate the building of a quick prototype using RISC-V cores on the VCU118. Chipyard was perfect, but required me to step up and learn Chisel and Rocket-chip tools to extend interconnection to…

chisel rocket-chip

asked Sep 13 '21 at 18:37

metzkorn

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Unrecognized opcode in creating custom RISC-V instruction

I've downloaded the rocket-chip repo and the corresponding rocket-tools repo. Everything works just fine when I initially build everything. I've created my own tightly coupled accelerator for the AES algorithm and want to test it using the custom-0…

riscv rocket-chip riscv32

asked May 12 '21 at 16:49

ttle

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Differences between LazyModule and LazyModuleImp

What are the differences between LazyModule and LazyModuleImp? Like the diplomacy demo under rocket-chip/doc says: The desired hardware for the module must be written inside LazyModuleImp. But considering following codes: class A(implicit p:…

riscv chisel rocket-chip firrtl

asked Apr 18 '21 at 14:36

Phantom

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how to understand the flip in autobundle（） and in makeios？

In LazyModule.scala , function AutoBundle() flip the Data(bundleIn) in dangleIn with flipped = true to make autoIO, while in Nodes.scala , function makeIOs() in class sourceNode flip the bundleOut to make IOs , why are they different? AutoBundle()…

scala io flip chisel rocket-chip

asked Apr 06 '21 at 06:42

李junhong

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How to link verilog blackbox to memory of rocketchip in chisel?

I am trying to attach a verilog module to rocketchip's memory. More precisely, I want to integrate a memory encryption engine as a blackbox. My idea is to link my verilog module to memAXI4Node of trait CanHaveMasterAXI4MemPort and io_axi4 node of…

chisel rocket-chip

asked Jan 29 '21 at 13:55

Jason Schneider

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multiple definition of `bitbang_swd' when building rocket-chip tools

I am trying to build rocket-chip tools according to instructions here: https://github.com/chipsalliance/rocket-tools/blob/master/README.md I face the following error: /usr/bin/ld:…

rocket-chip

asked Nov 27 '20 at 09:04

MatsB

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How to create memory in rocket-chip generator which will map as block ram in FPGA after synthesis?

I tried using Mem(1024,UInt(width=xLen)); but after synthesizing generated verilog file in Xilinx vivado.The memory mapped as distributed ram. It's really tough to understand and edit generated RTL file. Is there any explicit way to define memory…

riscv chisel rocket-chip

asked Nov 02 '20 at 13:04

Sanket Khandare

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How to synchronise a bundle between 2 clock domains in chisel

I'm trying synchronise a bundle of signals between 2 modules in different clock domain. I can do it by manually instantiating AsyncQueue between them , and also take care of hooking the clock & reset for each side. It seems like there is a seem-less…

chisel rocket-chip

asked Sep 17 '20 at 11:09

user3567895

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How do I make an individual Rocket tile asynchronous to the rest of the system

I have a multicore rocket-chip system. However I'd like one of those rocket tiles to be asynchronous from the rest. We're trying to do that with the following: class WithTilesCrossing extends Config((site, here, up) => { case RocketCrossingKey =>…

chisel rocket-chip

asked Mar 20 '20 at 10:14

jbaxter

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sbt.TrapExitSecurityException error message in from Chisel (rocket-chip)

I have gotten this fascinating exception (no additional backtrace, that's it) in rocket-chip Chisel elaboration. [info] [0.003] Elaborating design... ------------------------------------------------------------------------------ Error: Exception…

scala chisel rocket-chip

asked Mar 01 '20 at 20:20

user839768

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Questions tagged [rocket-chip]