Use for questions related to the Rocket-Chip SoC generator, used to generate and simulate multi-core RISC-V-based SOCs.
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Questions tagged [rocket-chip]
129 questions
0
votes
1 answer
Changing clocking in RocketSubsystemModuleImp from System.scala
I'm trying to alter the clocks and resets which go to each Rocket tile in my system.
At the moment I'm trying to do it like this. In Platform.scala I have some inputs declared in my PlatformIO (where $HARTS is our number of harts):
val hart_clocks =…
jbaxter
- 182
- 10
0
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0 answers
How do I run a single UnitTest from rocket-chip?
Specifically I'd like to run AXI4XbarTest from rocket-chip/src/main/scala/amba/axi4/Xbar.scala. It looks this test should be run by the regression tests, but if I go into the regression directory and run
export SUITE=UnittestSuite
make…
Ben Reynwar
- 1,547
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0
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1 answer
How to config xLen in rocket core?
I am trying to use rocket core as a baseline core and add some additional features for research purpose, but I can't find where or how to change the value "xLen".
Shibo Chen
- 77
- 6
0
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1 answer
Default cache parameters, how to change, limitation and more
I am new to rocket chip generator and still learning. First thing I want to know is how to parameterize l1 d cache. I did some research but it seems the info is not up to date. For example, in src/main/scala/config.scala, there is no d cache…
EricC
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- 1
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1 answer
What Linux entity is responsible for generating Illegal Instruction Traps?
I am working on a custom version of Rocket Chip that features some extra instructions that I would like to be properly handled by Linux. Although bare-metal programs using these instructions run fine, Linux makes the same benchmarks crash with…
Lucas Morais
- 25
- 3
0
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1 answer
How to create SystemC code for RISC-V Rocket-Chip?
Using the Rocket-Chip generator I can create Verilog output and the C++ emulator using the built version of Verilator.
I'd like to use Verilator to generate SystemC code using the default config Verilog output but getting errors.
I'm using the…
MikeG
- 11
- 2
-1
votes
1 answer
Configuration with APB fails to elaborate
I created the following configuration in Configs.scala:
class APBConfig extends Config(new WithDebugAPB ++ new TinyConfig)
I tried to build it with the following command:
/rocket/rocket-chip/vsim$…
Antti
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-2
votes
1 answer
Can you synthesize the RISC-V rocket chip test harness module?
After I setup the rocket-chip, it generated example top level Verilog. Can I synthesize the testharness.v module? I manually import the code into vivado, but got syntax error in SimDTM.v
(import "DPI-C" function int debug_tick)
vivado doesn't…
weaponwh
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-3
votes
1 answer
How to synthesis Rocket-Chip on Vivado?
I am trying to synthesis Rocket-Chip on Vivado. I was able to run a simulation on Vivado and get the required results. But, when I synthesis the same design and run the post synthesis simulation I dont get the same results. I used the 2 files…
hitoswal
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- 2